In-Gyu Baek

Realization of vertical resistive memory (VRRAM) using cost effective 3D process

Vertical ReRAM (VRRAM) has been realized with modification of Vertical NAND (VNAND) process and architecture as a cost-effective and extensible technology for future mass data storage. Dedicated ALD/CVD deposition and wet etching processes were developed to reproduce planar ReRAM properties in VRRAM structure. Multi-stack of VRRAM cell layers were fabricated at the same time using ALD TaOx/barrier layer/CVD TiN cell stacks. Oxidation control without intermixing has been found very critical in the vertical ReRAM cell process.

Stack friendly all-oxide 3D RRAM using GaInZnO peripheral TFT realized over glass substrates

This paper reports on new concept consisting of all-oxide-based device component for future high density non-volatile data storage with stackable structure. We demonstrate a GaInZnO (GIZO) thin film transistors (TFTs) integrated with 1D (CuO/InZnO)-1R (NiO) (one diode-one resistor) structure oxide memory node element. RRAM (Resistance Random Access Memory) has provided advantages in fabrication which have made these works possible. Therefore we also suggest methods and techniques for improving the distribution in bi-stable resistance characteristics of the NiO memory node. In order to fabricate stack structures, all device fabrication steps must be possible at low temperatures. The benefits provided by low temperature processes are demonstrated by our devices fabricated over glass substrates. Our paper shows the device characteristics of each individual component as well as the characteristics of combined select transistor with 1D-1R cell. XPS analysis of NiO RRAM resistance layer deposited by ALD confirms similar conclusions to previous reports of the importance of metallic Ni content in sputtered NiO for bistable resistance switching. Also we herein propose a generalized stacked-memory structure to minimize on-chip real estate to maximize integrated density.

Low power operating bipolar TMO ReRAM for sub 10 nm era

The bottle neck of ReRAM (Resistive RAM) for post-NAND storage application is high operational current [1,2]. Herein, we report a method to acquire low operational currents from a hetero structure ReRAM (AlOx/TiOx). The mechanism study of the hetero structure ReRAM reveals that the AlOx layer as a tunnel barrier is critical for switching, and thus switching parameters are governed by the properties of the AlOx layer. By tuning tunnel oxide properties along with adopting 5 nm sized “Dash BE” [3], operational currents of ≤ 10 µA have been achieved from this hetero structure device.

MRAM with lamellar structure as free layer

The key factors to improve the switching characteristics are systematically analyzed to develop high density MRAM with a reliable operating margin. We demonstrated that roughness control of MTJ films, choice of free layer materials with small Ms, and optimized cell shape can effectively suppress the switching distribution. As a novel free layer scheme, a lamellar structure is proposed and found to improve the switching characteristics by suppressing the grain growth in the ferromagnetic layer.