Moon-Sook Lee

Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses

Simple binary-TMO (transition metal oxide) resistive random access memory named as OxRRAM has been fully integrated with 0.18/spl mu/m CMOS technology, and its device as well as cell properties are reported for the first time. We confirmed that OxRRAM is highly compatible with the conventional CMOS process such that no other dedicated facility or process is necessary. Filamentary current paths, which are switched on or off by asymmetric unipolar voltage pulses, made the cell properties insensitive to cell or contact size promising high scalability. Also, OxRRAM showed excellent high temperature performance, even working at 300/spl deg/C without any significant degradation. With optimized TMO material and electrodes, OxRRAM operated successfully under 3V bias voltage and 2mA switching current at a TMO cell size smaller than 0.2/spl mu/m/sup 2/.

Al2O3 nanotubes and nanorods fabricated by coating and filling of carbon nanotubes with atomic-layer deposition

Aluminum oxide (Al2O3) nanotubes and nanorods were fabricated by coating and filling of multiwalled carbon nanotubes (MWNTs) with atomic-layer deposition (ALD). Al2O3 material was deposited on the MWNTs at a substrate temperature of 300°C using trimethylaluminum and distilled water. Transmission electron microscopy, high resolution transmission electron microscopy, energy-dispersive X-ray spectroscopy, and selected area electron diffraction of the deposited MWNTs revealed that amorphous Al2O3 material coats the MWNTs conformally and that this material fills the inside of the MWNTs. These illustrate that ALD has an excellent capability to coat and fill any three-dimensional shapes of MWNTs conformally without producing any crystallites.

Liquid delivery metal-organic chemical vapor deposition of Pb(ZrxTi1-x)O3 thin films for high-density ferroelectric random access memory application

The growth characteristics of Pb(ZrxTi1-x)O3 (PZT) thin films were investigated for application to high-density ferroelectric random access memories (FeRAM) devices. Films were grown by the liquid source metal-organic chemical vapor deposition (LS-MOCVD) method with tmhd-family precursors, such as Pb(tmhd)2, Zr(tmhd)2(OiPr)2 and Ti(tmhd)2(OiPr)2, dissolved in octane. Film deposition was mainly performed at 560°C, because it is the highest temperature at which bottom electrode contact could be maintained against oxidation in our capacitor over bit-line (COB) structure. The control of Pb precursor supply plays the most critical role in realizing a reliable process for PZT thin film deposition. We have monitored the changes in the microstructure and electrical properties of films on increasing the Pb precursor supply into the reaction chamber. Under optimized conditions, Ir/IrO2/PZT(100 nm)/Ir capacitor shows well-saturated hysteresis loops with a remanent polarization (Pr) of ~ 28 µC/cm2 and coercive voltage of 0.8 V at 2.5 V.

Integration and Electrical Properties of Carbon Nanotube Array for Interconnect Applications

Carbon nanotube (CNT) vertical integration and electrical properties are presented in full 6-inch wafer for interconnect applications. Series array of 1000 vias made of vertically grown CNTs is obtained with uniform electrical resistances within the wafer. Integration processes are implemented by following sequential steps: bottom electrode and via hole patterning, CNT growth and planarization, and top electrode patterning in a 6-inch wafer. Multiwall carbon nanotubes (MWNTs) are used for interconnection, titanium nitride for the bottom electrode, and aluminum with titanium adhesion layer for the top electrode. We have demonstrated well-defined CNT via series interconnection with 700 nm via diameters within the full wafer. Via resistance of 1.2 kΩ with CNT density of 2.7×1010/cm2is obtained with small resistance variation within the wafer, which also corresponds to 176 kΩ per one MWNT with 10 nm diameters. The possible approaches for further decrease of electrical resistance will be suggested.

Enhanced Retention Characteristics of Pb(Zr, Ti)O3 Capacitors by Ozone Treatment

Effects of ozone treatment and charged defects on retention characteristics of Ir/IrO2/Pb(Zr, Ti)O3 (PZT)/Pt/IrO2/Ir capacitors were systematically investigated. For these purposes, PZT thin films were exposed to ozone environment to promote enhanced surface oxidation. After baking the Ir/IrO2/PZT/Pt/IrO2/Ir capacitors at 125°C for 500 h, degradation of Qnv (non-volatile charge) value of the ozone-treated capacitors was approximately 17.6%, that is less than one fifth of that of the untreated capacitors. X-ray photoelectron spectroscopy (XPS) and Auger electron spectroscopy (AES) studies showed that the amount of oxygen-vacancies near the PZT surface was dramatically decreased by the ozone treatment. The Schottky barrier height of the ozone-treated capacitors increased when compared to that of the untreated capacitors (the Schottky barrier height of the untreated and the ozone-treated capacitor was 0.29 eV and 0.43 eV, respectively). Therefore, one can conclude that the retention characteristics seem to be closely associated with oxygen related defects near the ferroelectric/electrode interface and the control of the interface properties of PZT thin film is a key technology to pursue reliable function characteristics of ferroelectric random access memory (FRAM) devices.

Thermally Robust Multi-layer Non-Volatile Polymer Resistive Memory

The feasibility of the charge-transfer based polymer resistive memory as a future data storage device was tested using a thermally robust polyimide and PCBM composite film, available by low-cost solution processing. The prototype device with a simple 4F cross-point cell structure demonstrated basic non-volatile memory functions (> 1000 write/erase cycles and 1-week data retention in an ambient without encapsulation). Not only bi-polar but also uni-polar operation scheme with multi-level programming worked for the device. The cells on both the top and the bottom layers of a stacked device with additional heat budget of > 300 degC for 1 hour exhibited no degradation on the performance

Integration of ferroelectric random access memory devices with Ir/IrO2/Pb(ZrxTi1-x)O3/Ir capacitors formed by metalorganic chemical vapor deposition-grown Pb(ZrxTi1-x)O3

Metal organic chemical vapor deposition (MOCVD) of Pb(ZrxTi1-x)O3 (PZT) and its capacitor module process were established for ferroelectric memory device integration. The 130 nm-thick PZT films were deposited on Ir layers at 530°C or 550°C. The remnant polarization of the Ir/IrO2/PZT/Ir capacitors is in the range of 15 to 21 µC/cm2, and their leakage current is 10-5 A/cm2 at 2.5 V without additional annealing. The degradation in their switching endurance is less than 5% after 1010 cycles, indicating that the interfaces formed between the PZT and Ir layers can be optimized to improve their fatigue properties. To evaluate the capacitors on the devices, the conventional backend process was performed after encapsulating the capacitors with AlOx/TiOx layers located on the poly-Si plug. High charge separation and fully functional bit activities were obtained, demonstrating that this MOCVD-PZT process is a reliable integration scheme for high-density ferroelectric memory devices.

Plasma-assisted dry etching of ferroelectric capacitor modules and application to a 32M ferroelectric random access memory devices with submicron feature sizes

In the manufacturing of a 32M ferroelectric random access memory (FRAM) device on the basis of 0.25 design rule (D/R), one of the most difficult processes is to pattern a submicron capacitor module while retaining good ferroelectric properties. In this paper, we report the ferroelectric property of patterned submicron capacitor modules with a stack height of 380 nm, where the 100 nm-thick Pb(Zr, Ti)O3 (PZT) films were prepared by the sol-gel method. After patterning, overall sidewall slope was approximately 70° and cell-to-cell node separation was made to be 80 nm to prevent possible twin-bit failure in the device. Finally, several heat treatment conditions were investigated to retain the ferroelectric property of the patterned capacitor. It was found that rapid thermal processing (RTP) treatment yields better properties than conventional furnace annealing. This result is directly related to the near-surface chemistry of the PZT films, as confirmed by X-ray photoelectron spectroscopy (XPS) analysis. The resultant switching polarization value of the submicron capacitor was approximately 30 µC/cm2 measured at 3 V.

A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC)

The pad-polysilicon side contact (PSC) has drastically improved the performance of the partially-insulated bulk FinFET (Pi-FinFET). PSC enabled to dope a source and drain (S/D) of the fin structure uniformly from the top of the fin to the Pi layer. Since the uniform S/D increases effective channel width, the drivability was increased by 100% compared to the conventional bulk FinFET cell. Nevertheless, hot carrier (HC) lifetime was extended because the position of the highest electric field was nearer to the gate edge compared to the conventional. The total junction leakage current became 50% of the conventional due to the Pi layer. Undoped silicon selective epitaxial growth (SEG) buffered PSC could control gate induced drain leakage (GIDL) to the same level of conventional bulk FinFET. In addition, by optimizing fin height, 25% less word line capacitance (Cwl) was achieved. We place this Pi-FinFET with PSC is one of the promising candidates for the future FinFET DRAM cell technology.

Comparison of electrical characteristics of back- and top-gate Si nanowire field-effect transistors

Top-gate(TG) field effect transistors (FETs) with channels composed of Si nanowires were successfully fabricated in this study using photolithographic processes. In the TG FETs fabricated on oxidized Si substrates, the channels composed of Si nanowires with diameters of about 100 nm with natural SiO 2 . The surfaces of the Si nanowires with natural SiO2 were covered with the gate metal to form TG FETs.