In Man Kang

RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs

This paper presents a radio-frequency (RF) model and extracted model parameters for junctionless silicon nanowire (JLSNW) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a 3-D device simulator. JLSNW MOSFETs are evaluated for various RF parameters such as cutoff frequency fT, gate input capacitance, distributed channel resistances, transport time delay, and capacitance by the drain-induced barrier lowering effect. Direct comparisons of high-frequency performances and extracted parameters are made with conventional silicon nanowire MOSFETs. A non-quasi-static RF model has been used, along with SPICE to simulate JLSNW MOSFETs with RF parameters extracted from 3-D-simulated Y-parameters. The results show excellent agreements with the 3-D-simulated results up to the high frequency of fT.

The analysis of dark signals in the CMOS APS imagers from the characterization of test structures

The characteristics of dark signals have been investigated in the CMOS active pixel sensor (APS) with test structures fabricated using the deep-submicron CMOS technology. It is found that the periphery of the photodiode (PD) is the dominant source of dark currents in our test structure, and this factor is very sensitive to the distance between the sidewall of the shallow trench isolation and the n-type region of the PD. The dark currents from the transfer gate can be effectively reduced by the tail of p/sup +/ region on the surface of the transfer gate, and those from the floating diffusion (FD) node were estimated to be negligible in the normal operational mode. However, because of the enhanced thermal generation velocity caused by the severe process-induced damages, the FD node was considered as the main source of increased dark currents in the single frame capture mode. The characteristics of quantized dark currents causing the white pixels in the CMOS APS were examined using the dark current spectroscopy method. Three distinct deep-level bulk traps have been identified with the location in the silicon bandgap at |E/sub t/-E/sub i/|/spl sim/0.020 (eV), |E/sub t/-E/sub i/|/spl sim/0.082 (eV), and |E/sub t/-E/sub i/|/spl sim/0.058 (eV), and capture cross sections of 7.80/spl times/10/sup -15/ cm/sup 2/, 1.83/spl times/10/sup -13/ cm/sup 2/, and 1.46/spl times/10/sup -13/ cm/sup 2/ respectively.

Non-quasi-static small-signal modeling and analytical parameter extraction of SOI FinFETs

Accurate modeling and analytical parameter extraction of the non-quasi-static small-signal model of FinFETs are presented using a three-dimensional device simulator. Using simple Y- and Z-matrices calculations, the extrinsic gate-to-drain/source capacitance and source/drain resistance are de-embedded from the small-signal equivalent circuit. The analytical parameter extractions are performed by Y-parameter analysis after removing the extrinsic gate-to-drain/source capacitance and source/drain resistance. Accuracy of the model and extraction method is verified with the device-simulation data up to 700 GHz. Without any complex fitting and optimization steps, the total modeling rms error of the Y-parameter up to 700 GHz was calculated to be only 1.9 % in the saturation region and 2.1 % in the linear region. Also, the bias dependencies of the small-signal parameters are presented.

Analyses on Small-Signal Parameters and Radio-Frequency Modeling of Gate-All-Around Tunneling Field-Effect Transistors

The small-signal parameters of gate-all-around tunneling field-effect transistors (GAA TFETs) with different gate lengths were extracted and analyzed in terms of their gate capacitance, source-drain conductance, transconductance, distributed channel resistance, and inversion layer length. Because of the unique current drive and inversion layer formation mechanisms of a TFET compared to a conventional MOSFET, the gate-bias dependence values of the primary small-signal parameters of a GAA TFET also differ. Based on understanding these parameters, the high-frequency performances of GAA TFETs were investigated using a technology computer-aided design simulation. A nonquasistatic radio-frequency model was used to extract the small-signal parameters, which were verified up to 100 GHz. The modeling results showed excellent agreement with the Y-parameters up to the cutoff frequency fT.

Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation

In this study, we propose and characterize by simulation a silicon-compatible compound semiconductor tunneling field-effect transistor (TFET) based on germanium (Ge)/gallium arsenide (GaAs) heterojunction aiming the various integrated systems on silicon substrate. By introducing Ge as p+ source and GaAs as the high-mobility channel and n+ drain materials, we maximize on-state current (Ion) and minimize off-state current (Ioff) to obtain a TFET for high performance and low standby power capabilities. The effects of physical parameters such as aluminum content, source-gate overlap length, and gate workfunction on device performance were examined thoroughly. Further, we evaluate its radio frequency performance and confirm that it shows superb current and power gain characteristics.

Five-Step (Pad–Pad Short–Pad Open–Short–Open) De-Embedding Method and Its Verification

We present the method for five-step (pad-pad short-pad open-short-open) on-chip parasitic de-embedding. Its validation is verified by gate electrode resistance and input capacitance of transistors based on 45 -nm CMOS process. Optimized dummy structures to remove the parasitic components due to the pad and routing metal are proposed. Parameters extracted by the proposed method have excellent physical and theoretical trends.

Separate Extraction of Gate Resistance Components in RF MOSFETs

A simple and accurate method is presented for extraction of the gate resistance components of RF MOSFETs. Both the gate electrode resistance and the channel resistance were extracted separately. Also, the gate electrode resistance was separated into an external component and an internal component. The gate electrode resistance was extracted at OFF state, and the channel resistance was extracted with at ON state. The simple extraction methodology is applied to extract parameters from the measured S-parameters of RF MOSFETs that are fabricated with 130-nm CMOS technology.

AlGaN/GaN FinFET With Extremely Broad Transconductance by Side-Wall Wet Etch

AlGaN/GaN-based fin-shaped field-effect transistors with very steep side-wall have been fabricated by utilizing electron-beam lithography and subsequent anisotropic side-wall wet etch in tetramethyl ammonium hydroxide solution. The investigate device demonstrated extremely broad transconductance (gm) ranging from ~0 to ~8 V at VD = 10 V, which is essential for high linearity device performance. Pulse measurement showed that the device exhibits negligible gate lag, but still suffers from drain lag. The device with LGD of 17 μm exhibited excellent OFF-state characteristic with subthreshold swing of ~58 mV/decade, low OFF-state leakage current of ~10-12 A, and breakdown voltage of ~400 V at VG = -9 V.

Radio Frequency Performance of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

Radio frequency (RF) performances of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) have been compared with those of SiO2-only and high-k-only TFETs in terms of fT, fmax, gate capacitance, channel resistance, and transconductance. HG TFETs can have higher fT/fmax and smaller switching time than SiO2-only TFETs and high-k-only TFETs because they have higher gm and current drivability than SiO2-only TFET and smaller gate capacitance than high-k-only TFET.

Scalable Model of Substrate Resistance Components in RF MOSFETs With Bar-Type Body Contact Considered Layout Dimensions

Scalable model of substrate resistance components for radio-frequency MOSFETs fabricated by 65-nm CMOS technology with the bar-type body contact set in a horizontal direction to gate poly is presented. We consider various layout dimensions, such as channel length; unit finger width; number of fingers; distance between body contact and active region; and gate poly to gate poly distance on substrate resistance modeling. By using our model, the output admittance of the MOSFETs is well matched up to 50 GHz. The proposed models for substrate resistance are more accurate for devices with various geometries than previous substrate resistance models.