Seongjae Cho
Gachon University
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Publication
Featured researches published by Seongjae Cho.
Small | 2018
Sungjun Kim; Sunghun Jung; Min-Hwi Kim; Ying-Chen Chen; Yao-Feng Chang; Kyung-Chang Ryoo; Seongjae Cho; Jong-Ho Lee; Byung-Gook Park
A feasible approach is reported to reduce the switching current and increase the nonlinearity in a complementary metal-oxide-semiconductor (CMOS)-compatible Ti/SiNx /p+ -Si memristor by simply reducing the cell size down to sub-100 nm. Even though the switching voltages gradually increase with decreasing device size, the reset current is reduced because of the reduced current overshoot effect. The scaled devices (sub-100 nm) exhibit gradual reset switching driven by the electric field, whereas that of the large devices (≥1 µm) is driven by Joule heating. For the scaled cell (60 nm), the current levels are tunable by adjusting the reset stop voltage for multilevel cells. It is revealed that the nonlinearity in the low-resistance state is attributed to Fowler-Nordheim tunneling dominating in the high-voltage regime (≥1 V) for the scaled cells. The experimental findings demonstrate that the scaled metal-nitride-silicon memristor device paves the way to realize CMOS-compatible high-density crosspoint array applications.
Journal of Nanoscience and Nanotechnology | 2018
Bo Gyeong Kim; Jae Hwa Seo; Young Jun Yoon; Min Su Cho; Eunseon Yu; Jung-Hee Lee; Seongjae Cho; In Man Kang
In this study, one-transistor dynamic random-access memory (1T-DRAM) based on a symmetric double-gate Si junctionless transistor is proposed using technology computer-aided design simulation. The proposed device uses double gates that play different roles in realizing 1T-DRAM operation. Gate 1 is used as a switching node, and Gate 2 is used as a storage node. By controlling the different two gate workfunctions, a potential barrier is adjusted to store hole effectively. The operation characteristics were investigated regarding four different memory operation states to write 1, write 0, read, and hold. Also, the effects of two different gate workfunctions on sensing margin and retention characteristics are closely investigated. Through a set of optimally set gate workfunctions, 33 μA/μm of sensing margin and 38 ms of retention time have been obtained.
Solid-state Electronics | 2017
Min-Hwi Kim; Sungjun Kim; Suhyun Bang; Tae-Hyeon Kim; Dong Keun Lee; Seongjae Cho; Jong-Ho Lee; Byung-Gook Park
Journal of the Korean Physical Society | 2018
Eunseon Yu; Won-Jun Lee; Jongwan Jung; Seongjae Cho
Journal of Semiconductor Technology and Science | 2018
Eunseon Yu; Young-Min Kim; Junsoo Lee; Yongbeom Cho; Won Jae Lee; Seongjae Cho
Journal of Computational Electronics | 2018
Min-Hwi Kim; Sungjun Kim; Kyung-Chang Ryoo; Seongjae Cho; Byung-Gook Park
IEEE Transactions on Electron Devices | 2018
Eunseon Yu; Keun Heo; Seongjae Cho
IEEE Transactions on Electron Devices | 2018
Eunseon Yu; Won-Jun Lee; Jongwan Jung; Seongjae Cho
IEEE Electron Device Letters | 2018
Youngmin Kim; Min-Woo Kwon; Kyung-Chang Ryoo; Seongjae Cho; Byung-Gook Park
Solid-state Electronics | 2017
Tae-Hyeon Kim; Sungjun Kim; Hyungjin Myra Kim; Min-Hwi Kim; Suhyun Bang; Seongjae Cho; Byung-Gook Park