In-Soo Park

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Demand for high-speed DRAM in graphics application pushes a single-ended I/O signaling to operate up to 6Gb/s. To maintain the speed increase, the GDDR5 specification shifts from GDDR3/4 with respect to forwarded clocking, data training for write and read de-skewing, clock training, channel-error detection, bank group and data coding. This work tackles challenges in GDDR5 such as clock jitter and signal integrity.

A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

A 1.8V, 512Mbit Packet-based DRAM with 3.2Gbps/pin was designed for main memory of a game console and graphic application. To have lower power consumption and smaller area in clock generation and distribution, 3-row pad structure with reduced clock loading and PLL with loop zero from voltage offset are used. An analytical equation for estimating the input capacitance of pad with ODT (On-Die Termination) is also presented.

A novel robust TiN/AHO/TiN capacitor and CoSi/sub 2/ cell pad structure for 70nm stand-alone and embedded DRAM technology and beyond

For the first time, a novel robust (square-shape cylinder type) TiN/AHO (Al/sub 2/O/sub 3/-HfO/sub 2/)/TiN capacitor with Co-silicide on landing cell pad suitable for both stand-alone and embedded DRAMs are successfully developed with 88nm (pitch 176nm) feature size, which is the smallest feature size ever reported in DRAM technology, using ArF lithography for aiming 70nm stand-alone and embedded DRAM technology. The capacitor with Toxeq of 1.5nm and leakage current of less than 1 fA/cell is achieved. The cell contact resistance is greatly improved by using Co-silicidation on landing cell pad and metal storage node contact plug, which results in high performance.

A 5.0Gbps/pin packet-based DRAM with low latency receiver and process insensitive PLL

A 2.0V, 256Mbit packet-based DRAM with bandwidth of 10GB/s (5.0Gbps /spl times/ 16pin) was fabricated. To have high data bandwidth and stable clock generation, high performance input receiver and process insensitive PLL bias scheme were used. To increase the write speed of the cell array, write without 10 pre-charge scheme was employed. The power consumption and area of the chip are 2.4W and 7.2/spl times/10.2mm/sup 2/ respectively.

Highly electromigration-resistive via structure using Al-reflow for multi-level interconnection

A highly reliable double-level interconnection has been achieved by applying Al-reflow process to via level. The outgassing species from IMD materials were investigated by RGA and high temperature pre-degassing of IMD at 500 °C prior to Al deposition on vias is found to be essential to minimize via poisoning. When Al-reflow process was applied to vias, superior electromigration resistance of both via and metal lines was obtained with non-barrier structure, Al/Al, and thicker Ti barrier layer resulted in worse electromigration resistance. TEM micrographs of the via interfaces revealed that when Ti barrier layer was used in Al-reflow process, the high temperature reflow step produced agglomeration of Al×Ti at the via interface by the reaction between Ti and Al. The longer electromigration lifetime of Al-reflowed vias without Ti barrier layer is attributed to the elimination of Al step coverage as well as more homogeneous via interfaces.