Insoo Cho

The effect of FSG stability at high temperature on stress-induced voiding in Cu dual-damascene interconnects

The effect of FSG film properties as inter-metal dielectrics on stress-induced voiding (SIV) phenomena in Cu dual-damascene interconnects has been investigated with various FSG-films. HDPFSG and PEFSG2 showed less SIV failure than those of PEFSGI and 3. These behaviors of SIV according to FSG films agree well with desorbed amount of hydrogen, oxygen and fluorine ions from FSG films at high temperature over 400/spl deg/C. The result of SIMS analysis suggests that SIV phenomena are improved by application of stable FSG film without desorption at high temperature such as HDPFSG and PEFSG2 used in this work.

P-68: Numerical Optimization of Heat Sink Configuration for Avoiding Sound Noise Resonance in PDP PCB

PDP module mainly consists of panel and circuitries. Sound noise level in PDP modules rear side is relatively high rather than that in front side. It is due to sound noise caused from PCBs placed on rear side of PDP module. To analyze sound noise source and reduce sound noise level on PCBs of PDP module. Current wave form, voltage wave form and FFT spectrum are examined by oscilloscope and spectrum analyzer for PCB driving circuit board. Vibration frequency is measured by vibration sensor for parts on PCBs. It is found that peak frequency taken place from driver circuitry PCBs is as same as that of vibration on heat sink connected to MOSFET chip for heat dissipation of MOSFET chip on a PCB. Heat Sink is generally composed of aluminum metal and is also made large in height and area of heat dissipation to remove much more heat originated from MOSFET chip which is small in size on PCBs. Resonance noise between MOSFET chip and heat sink is enlarged much more through heat dissipation area of heat sink with a number of aluminum thin plate. Here, numerical approach of heat sink configuration is performed to avoid resonance frequency and reduce sound noise level on rear side of PDP module.

P‐69: Measurement and Simulation for Temperature Differences in a 42‐in. PDP Module

It is well known that panel glass of PDP module can be easily broken when the temperature difference on panel surface is over 20°C. Accordingly, it is necessary to improve heat dissipation of PDP module effectively in order that temperature difference of panel glass may be minimized after electrical discharge takes place between front panel and rear panel. Current heat dissipation scheme for PDP 42″ module consists of panels, chassis and TSSThermal Spread Sheet between panels and chassis. At present research, it is investigated through temperature measurement and numerical simulation how much TSS affects the temperature differences on front panel surface and it is also shown through measurement how much other kind of TSS can reduce both the temperature differences and highest temperature on front panel surface.

19.3: Hot Impinging Jet Approach for Drying Dielectric Layer of 42 in. PDP

Drying process of printed dielectric layer on PDP glass substrates has been taken through the drying furnace for around more than 40 minutes. Drying approach by hot air impinging jet on printed dielectric layer is introduced. It is at most taken 2 and half minutes to dry printed dielectric layer while glass substrate moves at moderate speed.

Impact of STI Gap-Fill Process Deposited By HDP-CVD in Flash Memory

The effects of shallow trench isolation (STI) gapfilling process deposited by high density plasma chemical vapor deposition (HDP-CVD) were investigated by comparing with TEOS+O3 undoped silicate glass (USG) process in NAND flash memory. HDP CVD oxide has been widely used for STI process because of its excellent gap-filling capability in relatively low temperature. However, it is well known that HDP-CVD process has problems caused by plasma-induced damage (PID) [1]. Thus thin thermal oxide was introduced as a buffer layer in order to minimize the plasma charging effect. In addition, there is also hydrogen related problem which is dissociated from SiH4 precursor in plasma. Hydrogen has both beneficial and deleterious effect to the gate integration [2]. The comparative sub-threshold swing degradation of the cell after F-N current stress of 0.13C/cm [3] is shown in Fig. 1. Initial swing is almost the same which indicates that PID during process is not dominant since the direct plasma damage was shielded by buffer oxide under layer. However, after stress, the swing of HDP-CVD gap-filled device is 20% more degraded than USG. The calculated interface state density (Dit) of the HDP-CVD is also 23% more than USG. It is insufficient to explain only with PID model. It was reported that hydrogen ions in plasma penetrate into underlying thermal oxide and they are drifted into the Si substrate by high electric field [4]. Although TEOS+O3 USG process also contains hydrogen species in precursor, the hydrogen atoms or ions have little kinetic energy to penetrate into underlying layers since there is no applied electric field or RF bias. Fig. 2. shows the hydrogen contents in both devices confirmed by thermal desorption spectroscopy (TDS) spectra after field recess process. HDP-CVD gap-filled device contains 50% more hydrogen concentration. It is well known that the role of atomic hydrogen is passivation of the Si dangling bonds in the Si/SiO2 interface (Si· + H2 → Si-H + H0) during the forming gas annealing (FGA) process. Simultaneously, the atomic hydrogen also depassivate the Si-H bonding (Si-H + H0 → Si· + H2) at room temperature [5,6]. As a results interface trap generation by atomic hydrogen depends on the ratio of passivation and depassivation. The HDP-CVD gap-filled device contains a large amount of hydrogen as we measured, and they can easily diffuse to tunnel oxide and degrade the cell transistors in flash memory. Fig. 3. shows average Vth shift of 64M cell array according to P/E cycling stress. The vth of HDP-CVD gap-filled device shifted 15% more than USG due to the oxide trap and interface trap generation by F-N current stress [7]. It is consistent with the swing degradation and the hydrogen depassivation model. We have demonstrated the effect of the plasmadeposited HDP-CVD STI gap-fill process which contains hydrogen species in the precursor and confirmed the degradation mechanism of the cell in flash memory. References

Carbonized surface curing for etch-back process

For flash memory below the 63nm node, two step Undoped Silicon Glass (USG) deposition and one step etch-back processes are applied in manufacturing processes to get good gap fill properties for Shallow Trench Isolation (STI) structures. The characteristics of the silicon surface after an etch-back process influences the following second USG deposition thickness and variation because the USG deposition process has high under-layer dependency and surface sensitivity. It can be reduced by changing some parameters during the deposition process like O3-TEOS ratio or temperature or pressure, but these methods also change the gap fill property and deposition rate [1]. So, we should find another method. This paper presents the detail studies of surface characteristics during processes that have been carried out to optimize the USG etch-back process.

Effects of patterns on corrosion in Cu CMP

Corrosion on specific Cu patterns was evaluated during Cu CMP. The corrosion was observed at isolated patterns and outer edge area of pad surrounded by oxide field after polishing and showed dependency on process. Two different commercial slurries were chosen and used for polishing after characterizing electrochemical and frictional properties. Stress simulations were conducted on these patterns. Higher stress was calculated on these patterns. The process temperature and friction behavior of Cu affected the magnitude of corrosion on Cu on these patterns.