Haebum Lee

3D strain measurement in electronic devices using through-focal annular dark-field imaging

Spherical aberration correction in high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) allows us to form an electron probe with reduced depth of field. Using through-focal HAADF imaging, we experimentally demonstrated 3D strain measurement in a strained-channel transistor. The strain field distribution in the channel region was obtained by scanning an electron beam over a plan-view specimen. Furthermore, the decrease in the strain fields toward the silicon substrate was revealed at different focal planes with a 5-nm focal step. These results demonstrate that it is possible to reconstruct the 3D strain field in electronic devices.

Hot carrier reliability characterization in consideration of self-heating in FinFET technology

A severity of hot carrier injection (HCI) in PFET becomes worse than NFET at elevated temperatures. This new observation is further found to be due to the coupled self-heating effects (SHE) during DC HCI stress (also a higher Ea in PFET HCI), rather than the negative bias temperature instability (NBTI) effect during HCI stress. Furthermore, in order to guarantee the precise estimation of HCI under circuit level AC condition, a new empirical HCI lifetime model decoupled from the SHE is proposed, which is further verified by the Si data from nanosecond pulsed waveform HCI stress and Ring Oscillator stress results.

Direct observation of nanometer-scale strain field around CoSi2/Si interface using scanning moiré fringe imaging

We report the use of scanning moire fringe (SMF) imaging through high-angle annular dark-field scanning transmission electron microscopy (STEM) to measure the strain field around a CoSi2 contact embedded in the source and drain (S/D) region of a transistor. The atomic arrangement of the CoSi2/Si (111) interface was determined from the high-resolution (HR)-STEM images, and the strain field formed around the S/D region was revealed by nanometer-scale SMFs appearing in the STEM image. In addition, we showed that the strain field in the S/D region measured by SMF imaging agreed with results obtained via peak-pairs analysis of HR-STEM images.

Largely defocused probe scanning transmission electron microscopy for imaging local modulation of strain field in a hetero interface

We present an innovative method for characterizing the strain field in three dimensions in a hetero interface. Largely defocused probe scanning transmission electron microscopy (LDP-STEM) was employed for imaging the inhomogeneous strain field in a germanium (Ge) layer deposited on a silicon (Si) substrate. In the LDP-STEM image, Ge-atomic columns that are relaxed or strained to the Si substrate in the Si/Ge hetero interface were observed to be distinguishable, allowing for the qualitative characterization of the coherency of the crystal growth. Our results revealed that the strain field is locally modulated along the in-plane direction in the Si/Ge hetero interface.

Investigation of logic circuit soft error rate (SER) in 14nm FinFET technology

This paper presents characterization results of soft error rate (SER) on logic circuits manufactured with 14 nm High-k/metal gate bulk FinFET technology. The FinFET SER advantage seen on SRAM was also validated on logic circuits (5-10X improvement). Alpha irradiation results reveal that charge collection only on NMOS on low critical charge can contribute to SEU. Adding NMOS on low critical charge can increase error rate, yet it can be easily mitigated by the design change. Design schemes for low-power has little impact to the SER. Single event transient on clock-line in 14 nm FinFET was substantially improved from planer-MOS.

Stress Analysis in a Si 1- x Ge x -Channel-Transistor by Scanning Moiré Fringe Imaging

We report on quantitative strain measurement of a Si_1-xGe_x-channel-transistor performed using the scanning moiré fringes that appear in high-angle annular dark-field scanning transmission electron microscopy. The strain fields in the Si1-xGex-channel region were measured along three orthogonal axes (X, Y, and Z). This three-axis strain measurement enabled us to calculate the stress applied in the channel region of the transistor, which was σ_xx = -4.3 GPa, σ_yy = -2.8 GPa, and σ_zz = -1.5 GPa for the longitudinal, transverse, and vertical directions relative to the current flow, respectively. The three-axis stress analysis demonstrated in this letter will enable comprehensive understanding of the strain engineering in electronic devices.

Reproducible strain measurement in electronic devices by applying integer multiple to scanning grating in scanning moiré fringe imaging

Scanning moire fringe (SMF) imaging by high-angle annular dark field scanning transmission electron microscopy was used to measure the strain field in the channel of a transistor with a CoSi2 source and drain. Nanometer-scale SMFs were formed with a scanning grating size of ds at integer multiples of the Si crystal lattice spacing dl (ds ∼ ndl, n = 2, 3, 4, 5). The moire fringe formula was modified to establish a method for quantifying strain measurement. We showed that strain fields in a transistor measured by SMF images were reproducible with an accuracy of 0.02%.

Scenario-based set-level HTOL test (ASH III) for product quality and reliability qualifications on high-speed APs

In a succession of the set level stress test for high speed mobile application processor (AP) reliability [1], At-Speed HTOL (ASH) incorporated by user conditions was employed to realistically project the field failure rate of product. Using the worst case-scenario test with different frequency and operation duty, the failure modes veiled behind the conventional HTOL can be surfaced and then reconciled, which is further evolved as a failure screening technique during volume production. In addition, the simulation methodology to determine product Vmin-guardband (GB) in pre-silicon phase is also developed and compared to the Product Vmin-GB results. The results of ASH with scenario test can extend our understanding of an effective methodology to ensure robust design from design for test (DFT) and to achieve decent field failure target.

Reliability characterizations of display driver IC on High-k/ metal-gate technology

Display Driver IC is used to operate the display panel of mobile devices, such as handheld smartphones and tablets. Low power consumption becomes very important in mobile segments, thus High-k (HK)/ metal-gate (MG) process was used to fabricate DDI products. In this paper, an abnormal leakage increase observed during HTOL will be discussed along with the physical mechanism and superb HTOL results after process fixes have been implemented. As result, final DDI product showed an excellent reliability results through 1500hrs of HTOL exceeding product end of life (EOL).

Mismatch circuit aging modeling and simulations for robust product design and pre-/post-silicon verification

As technology scales down, PMOS NBTI-induced mismatch, in addition to the NBTI mean-shifts and time0-Vt variation, is critical for designing circuitry having matched pair transistors, such as OP amplifier. This paper covers mismatch aging models incorporated into design simulation tool for PMIC products and used the Monte-Carlo simulation to consider process and systematic variations for robust design. Circuit simulation for PMIC OP Amp and its output characteristics were investigated and then further validated through the post-silicon HTOL stress. The pre-silicon simulation further enables to optimize HTOL stress conditions.