Hyeok-Sang Oh

Low Dielectric Constant 3MS α-SiC:H as Cu Diffusion Barrier Layer in Cu Dual Damascene Process

The primary candidate for the barrier/etch stop layer in damascene process is silicon nitride. However, silicon nitride has a high dielectric constant. To reduce the effective dielectric constant in the copper damascene structure, silicon carbide, which is prepared by plasma enhanced chemical vapor deposition (PECVD) using 3 methyl silane source (Z3MS), is studied for the dielectric copper diffusion barrier. The dielectric constant of PECVD α-SiC:H is varied from 4.0 to 7.0 and the fourier transform infrared (FTIR) spectra peak intensity ratio of Si–CH3 bond to Si–C is also examined. The reduction in dielectric constant of α-SiC:H using 3MS gas seems to be related to the decreased density upon incorporation of Si–CH3 groups. The value of capacitance with α-SiC is 8–10% lower than that with PECVD SiN. The leakage current with α-SiC:H barrier is lower by 1 order of magnitude than that with PECVD SiN barrier.

A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm DRAMs

Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si/sub 3/N/sub 4/, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) DRAMs.

High-density low-power-operating DRAM device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyond

For the first time, the DRAM device composed of 6F/sup 2/ open-bit-line memory cell with 80nm feature size is developed. Adopting 6F/sup 2/ scheme instead of customary 8F/sup 2/ scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F/sup 2/ accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F/sup 2/, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell V/sub th/ so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (sphere-shaped-recess-channel-array transistor) is introduced. It is the improved scheme of RCAT used in 8F/sup 2/ scheme. By adopting S-RCAT, V/sub th/ can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.

Mechanisms of stress-induced voids in multi-level Cu interconnects

One of the most serious problems in Cu-based multilevel integration is the failure in stacked vias caused by stress-induced voids. In this paper, the failure mechanism of the stacked via resistance is evaluated by analyzing the effects of the conditions of deposition and annealing in electroplated-Cu (EP-Cu) and the damascene structure scheme in a 64-bit RISC microprocessor with 7 copper layers. The stress-induced void is closely related to the stress change and the volume shrinkage of EP-Cu generated during deposition and annealing. The stacked via failures can be effectively suppressed with the application of two-step deposition and annealing in the EP-Cu process at the relatively low temperature of about 200/spl deg/C and the single damascene scheme for the layer of Via-5/Metal-6.

The effect of FSG stability at high temperature on stress-induced voiding in Cu dual-damascene interconnects

The effect of FSG film properties as inter-metal dielectrics on stress-induced voiding (SIV) phenomena in Cu dual-damascene interconnects has been investigated with various FSG-films. HDPFSG and PEFSG2 showed less SIV failure than those of PEFSGI and 3. These behaviors of SIV according to FSG films agree well with desorbed amount of hydrogen, oxygen and fluorine ions from FSG films at high temperature over 400/spl deg/C. The result of SIMS analysis suggests that SIV phenomena are improved by application of stable FSG film without desorption at high temperature such as HDPFSG and PEFSG2 used in this work.

Cost-effective "BARC/resist-via-fill free" integration technology for 0.13 /spl mu/m Cu/low-k

Demonstrates the first successful integration scheme free of BARC/resist via-fill that not only significantly simplifies the overall process complexity, but also reduces cost and process instabilities by employing an OSG (k=2.9)/ HDP-FSG dual ILD structure in conjunction with our proprietary plasma induced polymeric etch stopper (PIPS) in a 7-metal level 0. 13 /spl mu/m design node. The via poisoning problem and low selectivity of etch stopper were overcome by optimizing ILD structure and PIPS etch process. The electrical characteristics and reliability results indicate that the current integration scheme is highly manufacturable.