Nikolaos Fasarakis

Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

Simple analytical models for the front and back gate threshold voltages and ideality factors with back gate control of lightly doped short channel fully depleted silicon-on-insulator ultrathin body and buried oxide thickness MOSFETs have been developed based on the minimum value of the front and back surface potentials. The threshold voltage and ideality factor models of the front and back gates have been verified with numerical simulations in terms of the device geometry parameters and the applied bias voltages, as well as with experimental results for devices with channel length down to 17 nm. Good agreement between the model, simulation, and experimental results were obtained by calibrating the minimum carrier charge density adequate to achieve the turn-on condition.

A Lambert-Function Charge-Based Methodology for Extracting Electrical Parameters of Nanoscale FinFETs

We developed a new Y-based methodology for extracting the electrical parameters in modern nanoscale double-gate and triple-gate FinFET devices. Using the drain-current equation in the linear region, which involves the Lambert W -function of the charge at the source, the nonlinear Y-function in these devices is reduced to the linear one of a traditional long-channel MOSFET. The derived new Y-function can be readily applied and evaluate all electrical parameters in a traditional fashion, since all related curves are now linear and easily extrapolated. The present methodology for extracting the electrical parameters was verified in both simulated and experimental nanoscale FinFETs, demonstrating its simplicity and good accuracy.

Compact Modeling of Nanoscale Trapezoidal FinFETs

An analytical compact model for the drain current of undoped or lightly doped nanoscale FinFETs with trapezoidal cross section is proposed. The compact model of rectangular FinFETs is extended to trapezoidal FinFETs using equivalent nonplanar device parameters and corner effects. The model has been validated by comparing the results with those of 3-D numerical device simulations. The very good accuracy of the drain current and transcapacitances makes the proposed model suitable for implementation in circuit simulation tools.

Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs

A charge-based compact capacitance model has been developed describing the capacitance-voltage characteristics of undoped or lightly doped ultra-scaled triple-gate fin field-effect transistors. Based on a unified expression for the drain current and the inversion sheet charge density, i.e., the Ward-Dutton linear-charge-partition method and the drain current continuity principle, all trans-capacitances are analytically derived. The developed capacitance model is valid in all regions of operation, from the subthreshold region to the strong inversion region and from the linear region to the saturation region. The gate and source trans-capacitances have been validated by 3-D numerical simulations over a large range of device dimensions. The parameters of the capacitance model can be used to accurately predict the transfer and output characteristics of the transistors, making this compact model very useful for circuit designers.

Flicker noise in n-channel nanoscale tri-gate fin-shaped field-effect transistors

In n-channel nanoscale tri-gate fin-shaped field-effect transistors with high-k gate dielectric stack, the 1/f noise is investigated, ascribed to the carrier number fluctuations with correlated mobility fluctuations. The overall results show that the gate dielectric trap density is uniform in both top-gate and side-gates and the product Ω=αscμeffCox of the Coulomb scattering coefficient αsc, the effective carrier mobility μeff and the gate oxide capacitance per unit area Cox increase with decreasing the fin thickness due to enhancement of side-gates interface roughness effects.

Hot carrier degradation modeling of short-channel n-FinFETs suitable for circuit simulators

Figure 1(a) shows the degradation of the transfer characteristics of a typical FinFET with W_fin = 10 nm, measured at V_d = 0.03 V after HC stress at V_stress = 1.8 V for different stress times. The degradation of the device parameters V_t, η and on-state drain current is clearly observed. The positive V_t shift indicates the built-up of a negative charge in the gate dielectric. The negative charge can result either from electron trapping in the gate dielectric or from generation of acceptor-type interface traps. Figure 1(b) shows the transconductance g_m degradation during HC stress. Degradation of the maximum g_m is observed attributed to the interface degradation, with a simultaneous parallel g_m shift due to charge injection into the gate dielectric bulk defects [4]. Using the relation SS=(kT/q).qD_it/C_ox for the subthreshold slope SS, where C_ox is the gate oxide capacitance and kT is the thermal energy, from figure 1(a) the extracted interface trap density D_it changes from 4×10¹² to 5.5×10¹²cm^-2eV^-1.

An analytical model for the CMOS inverter

A new analytical model for the CMOS inverter is introduced. This model results by solving analytically the differential equation which describes the inverter operation. It uses new simplified transistor current expressions which are developed taking into account the nanoscale effects and also considering temperature as a parameter. Expressions for the output voltage are derived, which are then used for capturing the output and supply currents, making the model compatible with CCS technology requirements. The proposed model is parametric according to the input signal slew, output load, transistor widths, supply voltage, temperature and process parameters. It presents an average error less than 3% for the typical case.

Variability analysis - prediction method for nanoscale triple gate FinFETs

Our analytical compact model for the drain of undoped or lightly doped nanoscale FinFETs has been expanded in order to predict and decompose variability in the electrical characteristics of FinFETs. The model has been evaluated by comparison to TCAD simulated devices with predefined variability. Successful application to experimental data of FinFETs with fin width Wfin= 15 nm, gate length LG =30 nm, equivalent gate oxide thickness tox = 1.7 nm and fin height Hfin= 65 nm, has attributed their behavior to geometrical variations (σLG = 3.85 nm, σWfin = 1.80 nm) and variability in the metal gate work function (σΦm = 48.1 eV).

Compact modeling of nano-scale trapezoidal cross-sectional FinFETs

Analytical compact model for the drain current and trans-capacitances of undoped or lightly doped nanoscale FinFETs with trapezoidal cross section is presented. The compact model of rectangular FinFETs is applied in trapezoidal FinFETs using the concept of the equivalent device parameters. The model is compared with the results of three-dimensional numerical device simulations. The overall results reveal the very good accuracy of the proposed compact model, making it suitable for circuit design simulation tools.