A. Tsormpatzoglou

Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

A simple analytical expression of the 2-D potential distribution along the channel of silicon symmetrical double-gate (DG) MOSFETs in weak inversion is derived. The analytical solution of the potential distribution is compared with the numerical solution of the 2-D Poissons equation in terms of the channel length L, the silicon thickness t Si, and the gate oxide thickness t OX. The obtained results show that the analytical solution describes, with good accuracy, the potential distribution along the channel at different positions from the gate interfaces for well-designed devices when the ratio of L/t Si is ges 2-3. Based on the 2-D extra potential induced in the silicon film due to short-channel effects (SCEs), a semi-analytical expression for the subthreshold drain current of short-channel devices is derived. From the obtained subthreshold characteristics, the extracted device parameters of the subthreshold slope, drain-induced barrier lowering, and threshold voltage are discussed. Application of the proposed model to devices with silicon replaced by germanium demonstrates that the germanium DG MOSFETs are more prone to SCEs.

Threshold Voltage Model for Short-Channel Undoped Symmetrical Double-Gate MOSFETs

A simple threshold voltage model of an undoped symmetrical double-gate MOSFET has been developed, based on an analytical solution of Poissons equation for the potential distribution. The model has been verified by comparing the threshold voltage roll-off with the channel length with simulation results for different silicon thicknesses, gate oxide thicknesses, and drain voltage values. Good agreement between model and simulation results is obtained by calibrating the minimum carrier charge sheet density adequate to achieve the turn-on condition.

Semianalytical Modeling of Short-Channel Effects in Lightly Doped Silicon Trigate MOSFETs

A simple analytical expression of the 3-D potential distribution along the channel of lightly doped silicon trigate MOSFETs in weak inversion is derived, based on a perimeter-weighted approach of symmetric and asymmetric double-gate MOSFETs. The analytical solution is compared with the numerical solution of the 3-D Poissons equation in the cases where the ratios of channel length/silicon thickness and channel length/channel width are ges 2. Good agreement is achieved at different positions within the channel. The perimeter-weighted approach fails at the corner regions of the silicon body; however, by using corner rounding and undoped channel to avoid corner effects in simulations, the agreement between model and simulation results is improved. By using the extra potential induced in the silicon film due to short-channel effects, the subthreshold drain current is determined in a semianalytical way, from which the subthreshold slope, the drain-induced barrier lowering, and the threshold voltage are extracted.

Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

Effect of Localized Interface Charge on the Threshold Voltage of Short-Channel Undoped Symmetrical Double-Gate MOSFETs

An analytical threshold-voltage model of short-channel undoped symmetrical double-gate metal-oxide-semiconductor field-effect transistors including positive or negative interface charges near the drain is presented. The threshold-voltage model is derived based on an analytical solution for the potential distribution along the channel in the subthreshold region. Both potential and threshold-voltage models are compared with the Atlas simulation results, with variables being the device dimensions, the interface-charge region length and the interface-charge density. A good agreement between the model and simulation results has been observed by calibrating as a constant parameter the gate voltage included in the position of the minimum potential and the carrier charge-sheet density at the potential minimum that is adequate to achieve the turn-on condition.

A compact drain current model of short-channel cylindrical gate-all-around MOSFETs

A fully analytical potential model, valid in the weak inversion regime of short-channel cylindrical gate-all-around (GAA) MOSFET, is proposed. The model derivation is based on a previous analytical expression for tetragonal GAA MOSFET and the rotational symmetry of the tetragonal cross section. Device simulations were performed to verify that the potential distribution along the channel is properly described in all positions within the silicon body. Using the potential model, analytical expressions for the threshold voltage, subthreshold swing and drain-induced barrier lowering have been derived. Including the short-channel effects within an existing model for the subthreshold leakage current and an analytical drain current model of long-channel devices in strong inversion, a compact drain current model has been derived describing with good accuracy the transfer and output characteristics of short-channel GAA MOSFETs in all regions of operation.

Analytical surface-potential-based drain current model for amorphous InGaZnO thin film transistors

A fully analytical surface-potential-based drain current model for amorphous InGaZnO (α-IGZO) thin film transistors (TFTs) has been developed based on a Gaussian distribution of subgap states, with the central energy fixed at the conduction band edge, which is approximated by two exponential distributions. This model includes both drift and diffusion components to describe the drain current in all regions of operation. Using an empirical mobility relationship that depends on both horizontal and vertical electric field, it is demonstrated that the model describes accurately the experimental transfer and output characteristics, making the model suitable for the design of circuits using α-IGZO TFTs.

Characterization of traps in the gate dielectric of amorphous and nanocrystalline silicon thin-film transistors by 1/f noise

The low frequency noise technique is used to obtain the volume profile of traps in the SiNx gate dielectric of hydrogenated amorphous silicon (a-Si:H) and nanocrystalline silicon (nc-Si:H) thin film transistors (TFTs). In both a-Si:H and nc-Si:H TFTs, within the range of probing depth in the gate dielectric, the traps have a uniform spatial distribution which is consistent with the observed pure 1/f noise. The experimental results show that the gate dielectric trap properties near the interface are dependent on the channel material with the trap density in nc-Si:H TFTs being much smaller in comparison with the a-Si:H TFTs.

Origin of Low-Frequency Noise in the Low Drain Current Range of Bottom-Gate Amorphous IGZO Thin-Film Transistors

The low-frequency noise of bottom-gate amorphous IGZO thin-film transistors is investigated in the low drain current range. The noise spectra show generation-recombination (g-r) noise at drain currents Id <; 5 nA, attributed to bulk traps located in a thin layer of the IGZO close to the conducting channel. At higher drain currents, a pure 1/f noise is observed. It is shown that the carrier number fluctuations are responsible for the 1/f noise due to trapping/detrapping of carriers in slow oxide traps, located near the interface with uniform spatial distribution.

A Lambert-Function Charge-Based Methodology for Extracting Electrical Parameters of Nanoscale FinFETs

We developed a new Y-based methodology for extracting the electrical parameters in modern nanoscale double-gate and triple-gate FinFET devices. Using the drain-current equation in the linear region, which involves the Lambert W -function of the charge at the source, the nonlinear Y-function in these devices is reduced to the linear one of a traditional long-channel MOSFET. The derived new Y-function can be readily applied and evaluate all electrical parameters in a traditional fashion, since all related curves are now linear and easily extrapolated. The present methodology for extracting the electrical parameters was verified in both simulated and experimental nanoscale FinFETs, demonstrating its simplicity and good accuracy.