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Featured researches published by Irenee Pages.
international symposium on power semiconductor devices and ic s | 1999
M. Zitouni; F. Morancho; P. Rossel; H. Tranduc; Juan Buxo; Irenee Pages
In this paper, a new concept of lateral DMOSFET for smart power integrated circuits is proposed, in which a vertical trench is used under the gate end in the drift region.
Microelectronics Journal | 1999
M Zitouni; F. Morancho; H. Tranduc; P. Rossel; Juan Buxo; Irenee Pages; S Merchant
In this paper, a new concept of lateral DMOSFET for medium voltage (<100 V) smart power integrated circuits is proposed. These structures present a trench in the drift region filled with oxide or with oxide and polysilicon. These structures called LUDMOSFET feature a reduced specific on-resistance and enhanced breakdown voltage. For example, for a breakdown voltage of 50 V, the specific on-resistance is 1.2 mΩ cm 2 in the conventional LDMOSFET, 0.8 mΩ cm 2 in the LUDMOS without polysilicon (i.e. 30 percent reduction) and 0.6 mΩ cm 2 in the LUDMOS with polysilicon (i.e. 50 percent reduction). They are technologically compatible with advanced CMOS processes using trench isolation.
international symposium on power semiconductor devices and ic s | 1998
D. Farenc; G. Charitat; P. Dupuy; T. Sicard; Irenee Pages; P. Rossel
This paper explores the energy capability of an integrated clamped lateral power MOS transistor. The energy capability is determined by switching the device on an inductive load. Experimental results show that the rating of the transistor in terms of energy has to be given along with the drain voltage applied during the transient regime. If the clamp voltage increases, the energy capability decreases. This is explained by the presence of a parasitic NPN transistor in the LDMOS transistor. A specific structure is designed in order to determine the energy capability that would correspond to a purely thermal failure mechanism.
european solid-state device research conference | 1997
Arlette Marty-Blavier; Didier Farenc; Thierry Sicard; Gisele Blanc; Irenee Pages
This paper describes a technology that offers a wide variety of devices: bipolar NPN and PNP transistors, low voltage and medium voltage CMOS, high voltage PMOS, power DMOS, zener diodes, resistors and capacitors. Device characteristics are presented. It is demonstrated that the DMOS device is optimized in terms of energy capability and On-resistance. Considering the low mask count, this technology is cost effective and device characteristics make it attractive for a wide range of Smart Power applications.
international symposium on power semiconductor devices and ic s | 2000
Irenee Pages; B. Baird; J. Wang; T. Sicard; J.M. Dorkel; P. Dupuy; P. Lance; E. Huynh; Y. Chung
Cost effective automotive applications and the related circuit designs are requiring new SMARTMOS/sup TM/ technology extensions to manage energy capability and metal debiasing in smart power devices. A thick copper metallization scheme, POWER COPPER, has been integrated and characterized in the circuit design of two electronic modules for automotive applications.
Archive | 1997
Patrice Parris; Yee-Chaung See; Irenee Pages; Juan Buxo; Eric Scott Carman; Thierry Sicard; Quang Xuan Nguyen
Archive | 2001
Andre Peyre-Lavigne; Irenee Pages; P. Rossel; F. Morancho; Nathalie Cezac
Archive | 1995
Barbara Vasquez; Irenee Pages; E. James Prendergast
Archive | 1989
Anthony Polito; Irenee Pages
Archive | 1994
Irenee Pages; Francesco D'Aragona; James A. Sellers; Raymond C. Wells