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Dive into the research topics where Juan Buxo is active.

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Featured researches published by Juan Buxo.


international symposium on power semiconductor devices and ic s | 1999

A new concept for the lateral DMOS transistor for smart power IC's

M. Zitouni; F. Morancho; P. Rossel; H. Tranduc; Juan Buxo; Irenee Pages

In this paper, a new concept of lateral DMOSFET for smart power integrated circuits is proposed, in which a vertical trench is used under the gate end in the drift region.


Microelectronics Journal | 1999

A new lateral power MOSFET for smart power ICs : the LUDMOS concept

M Zitouni; F. Morancho; H. Tranduc; P. Rossel; Juan Buxo; Irenee Pages; S Merchant

In this paper, a new concept of lateral DMOSFET for medium voltage (<100 V) smart power integrated circuits is proposed. These structures present a trench in the drift region filled with oxide or with oxide and polysilicon. These structures called LUDMOSFET feature a reduced specific on-resistance and enhanced breakdown voltage. For example, for a breakdown voltage of 50 V, the specific on-resistance is 1.2 mΩ cm 2 in the conventional LDMOSFET, 0.8 mΩ cm 2 in the LUDMOS without polysilicon (i.e. 30 percent reduction) and 0.6 mΩ cm 2 in the LUDMOS with polysilicon (i.e. 50 percent reduction). They are technologically compatible with advanced CMOS processes using trench isolation.


international symposium on power semiconductor devices and ic's | 1992

Comparison between biased and floating guard rings used as junction termination technique

V. Macary; G. Charitat; Marise Bafleur; Juan Buxo; P. Rossel

Using biased rings instead of floating rings as power devices termination is shown to offer several advantages such as an easy design and simple implementation. An analytical optimization of the biased ring structure is proposed and shown to be in good agreement with 2D simulations. A comparison between biased and floating rings is made, from the point of view of the tolerance on geometrical parameters and space consumed by these structures. Biased structures exhibit a weak dependance on inter-ring distance and interface states as compared to floating structures.


Microelectronic Engineering | 1995

The effect of doping profile variations upon deep submicrometer MOSFETs

J.R. Brews; Juan Buxo

Abstract The variations in current induced by variations in the (horizontal) doping profile between channel and drain or source can be described in terms of variations in the effective channel length L EFF induced by the variations in the doping profile of source or drain. Sensitivity to profile variations becomes severe as L EFF → 0, because the current in the L EFF → 0 regime depends exponentially on the barrier potential. Likewise, because of the exponential dependence of current on potential in the subthreshold region, sensitivity is particularly strong in subthreshold for variations in the (vertical) channel profile that determines the device threshold and turn-off. The centroid of the vertical profile must be controlled to sub-Debye length accuracy to keep subthreshold current variations below a few percent.


Archive | 1997

Single level gate nonvolatile memory device and method for accessing the same

Patrice Parris; Yee-Chaung See; Irenee Pages; Juan Buxo; Eric Scott Carman; Thierry Sicard; Quang Xuan Nguyen


Archive | 1994

Method of fabricating an insulated gate semiconductor device

Robert B. Davies; Peter J. Zdebel; Juan Buxo


Archive | 1994

Insulated gate semiconductor device and method of fabricating

Robert B. Davies; Peter J. Zdebel; Juan Buxo


Archive | 1997

Insulated gate field effect transistor structure having a unilateral source extension

Juan Buxo; Diann Dow; Vida Ilderem; Thomas E. Zirkle


Archive | 1999

Semiconductor device and a method of operation the same

Danny Pak-Chum Shum; Juan Buxo; John P. Hansen; Scott W. Krueger; James D. Burnett; Eric J. Salter


Archive | 1997

Transistor protection circuit and method

Juan Buxo; Andreas A. Wild; Gary H. Loechelt; Thomas E. Zirkle; E. James Prendergast; Patrice Parris

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