Itaru Nonomura

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM

This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling. A 90nm CMOS 8-core processor, back-grinded to a thickness of 50µm, is mounted face down on a package by C4 bump. A 65nm CMOS 1MB SRAM of the same thickness is glued on it face up, and the power is provided by conventional wire-bonding. The two chips under different supply voltages are AC-coupled by inductive coupling that provides a 19.2Gb/s data link. Measured power and area efficiency of the link is 1pJ/b and 0.15mm2/Gbps, which is 1/30 and 1/3 in comparison with the conventional DDR2 interface respectively [1]. The power efficiency is improved by narrowing a transmission data pulse to 180ps. Reduced timing margin for sampling the narrow pulse, on the other hand, is compensated against timing skews due to layout and PVT variations by a proposed 2-step timing adjustment using an SRAM through mode. All the bits of the SRAM is successfully accessed with no bit error under changes of supply voltages (±5%) and temperature (25°C, 55°C).

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link

This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pj/b and 0.15 mm2 /Gbps, respectively, which are the same as those of two-chip integration.

Peach: A Multicore Communication System on Chip with PCI Express

The PCI Express Adaptive Communication Hub (Peach) is an eight-core communication system on chip with four PCI Express Revision 2.0 ports, each with four lanes. Peach realizes a high-performance, power-aware, highly dependable network that uses PCI Express not only for connecting peripheral devices but also as a communication link between computing nodes. This approach opens up new possibilities for a range of communications.

An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs

InfiniBand is widely used as a low-latency and high-bandwidth network for highperformance computing (HPC) clusters [1]. However, power consumption and system cost become large in exchange for high performance on small-scale clusters or embedded systems. To cope with these problems, we use PCI Express (PCIe) [2] technology as a direct communication link between computing nodes. Point-to-point bidirectional packet communication is implemented by using PCIe basic operations such as memory read/write between the host and the device. Therefore, PCIe technology can be applied to inter-node communication and thereby eliminate communication overhead and extra power consumption caused by the protocol conversion via the network device [3].

An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller

An 80 Gbps dependable communication SoC with four 4X PCIe Rev.2.0 ports has been developed that acts as a communication link with high transfer capability. By using the PCIe I/F, the SoC can address two computing nodes as peers, breaking the traditional PCIe limit of only linking to a single master processor. The SoC also employs an intelligent ICU that supports an initiate data transfer function and offloads interrupt services from the CPUs. This function can dramatically reduce processing time by 20% compared to using CPU interrupt handlers. To achieve a highly dependable network, the multicore processor continuously monitors the network status and operates the fault handling efficiently by using IRQ affinity. Our SoC achieves the power consumption of 3.2W at 80 Gbps and the power efficiency of 0.04 W/Gbps, which is 51.5% more power efficiency than 4X InfiniBand.

Design of a 90nm 4-CPU 4320MIPS SoC with individually managed frequency and 2.4GB/s multi-master on-chip interconnect

We have developed a 97.6 mm2 SoC that includes four SuperHtrade architecture CPUs and a DDR-2 controller with 90-nm CMOS for high-performance embedded applications. These four 600 MHz CPUs are identical and each has a floating point unit, 32/32 KB cache memory, and 152 KB local memory. CPUs totally achieve performance of 4320MIPS. Main on-chip 300 MHz 64-bit bus manages processors access and another dedicated connection holds cache coherency operation. Considering varying processing load, this chip targets both low power consumption (proportional to processing load), and constant on-chip bandwidth. Each processor can be operated different frequencies while keeping on-chip bus frequency constant. With utilizing this individual core clock distribution scheme, the following designs have been developed: (i) frequency transition control that permits on-chip bus access of other bus master, (11) light-sleep mode that maintains cache coherency control, (iii) cache snoop control logic that holds cache coherency between multiple frequency processors. The main on-chip interconnect (bus) connects four-processor and other on-chip IPs. The numbers of access master and access slave increase due to processor number. Standard-Vth (against high-Vth) cell usage and layout control achieved 300-MHz multi-master operation.