Makoto Saen

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM

This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling. A 90nm CMOS 8-core processor, back-grinded to a thickness of 50µm, is mounted face down on a package by C4 bump. A 65nm CMOS 1MB SRAM of the same thickness is glued on it face up, and the power is provided by conventional wire-bonding. The two chips under different supply voltages are AC-coupled by inductive coupling that provides a 19.2Gb/s data link. Measured power and area efficiency of the link is 1pJ/b and 0.15mm2/Gbps, which is 1/30 and 1/3 in comparison with the conventional DDR2 interface respectively [1]. The power efficiency is improved by narrowing a transmission data pulse to 180ps. Reduced timing margin for sampling the narrow pulse, on the other hand, is compensated against timing skews due to layout and PVT variations by a proposed 2-step timing adjustment using an SRAM through mode. All the bits of the SRAM is successfully accessed with no bit error under changes of supply voltages (±5%) and temperature (25°C, 55°C).

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link

This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pj/b and 0.15 mm2 /Gbps, respectively, which are the same as those of two-chip integration.

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth

A 0.4mm2 SoC resource manager controls operating frequency and allocates data bandwidth using various monitored information such as temperature, frequency of IP blocks and number of operations executed. Results show an increase of allowable temperature range by 30degC for real-time operations of two processor cores and two media processing cores. The design is fabricated in an 8M 90nm CMOS process

Action-Intention-Based Grasp Control With Fine Finger-Force Adjustment Using Combined Optical-Mechanical Tactile Sensor

This paper presents a control method that makes it possible for a home-use manipulation system to easily grasp objects with various weights and hardnesses. To provide easy operability for nonprofessional persons, an action-intention-based man-machine interaction method was developed. To enable the fine finger-force control required for grasping various objects, a combined optical-mechanical tactile sensing method with high-sensitivity slip detection was also developed. In addition, as a platform for manipulation systems with many sensors, a hierarchical multiprocessor controller was built. The developed methods were evaluated experimentally by using a prototype manipulation system consisting of a robotic hand and a user interface. The evaluation results demonstrate that the manipulator system can be used to easily grasp various objects, such as a rolled-up paper towel (weighing 4 g) and a clay-filled cardboard tube (weighing 500 g). Operability in remote control was also evaluated. The developed methods make it possible to fine-tune the finger force according to target object on the basis of tactile sensing information.

A low-power wide-range clock synchronizer with predictive-delay-adjustment scheme for continuous voltage scaling in DVFS control

A “wide-range voltage-and-frequency clock synchronizer” (WRCS) for maintaining synchronization during voltage-scaling transition during dynamic voltage-and-frequency scaling (DVFS) was developed. The key feature of the WRCS is so-called predictive-delay-adjustment (PDA) scheme based on a relative skew measure. The PDA scheme reduces the area of the WRCS by 77%. The area of the fabricated WRCS in a 40-nm CMOS is only 5.65×10−3 mm2. It was demonstrated for the first time that measured jitter is suppressed to less than 6.8% of clock period in the case of wide-range voltage variation (0.8–1.55 V) and wide frequency range (100 MHz–1 GHz). Moreover, current dissipation of the WRCS is only 0.48 mA at 1.1-V 100-MHz operation.

Scalable robotic-hand control system based on a hierarchical multi-processor architecture adopting a large number of tactile sensors

A robotic-hand controller with operating performance scalable according to the number of connected tactile sensors was developed. To eliminate performance bottlenecks that appear with increasing number of sensors, the controller architecture adopts multiple processors connected in a loosely-coupled hierarchical structure. Moreover, to maximize operation throughput of the system, a technique for gathering sensor data while all components operate asynchronously was also developed. A prototype robotic-hand system based on this architecture was constructed. The system experimentally demonstrated 62%-reduced control latency and 6.5-times faster sensor-data processing, thus achieving seven times greater performance scalability as compared with a conventional controller architecture. As a result, the proposed architecture enables the robotic-hand system to grasp objects with different weights and hardnesses.

Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration

In this paper, two designs of a 3D interconnection architecture for stacked processor-memory large-scale integrations (LSIs) were investigated. With consideration given to stacking formation, a hierarchical 3D interconnection architecture with a tightly coupled processor-memory stacking configuration is proposed for achieving both higher throughput per unit area and lower power consumption in the vertical communications. Compared with a baseline stacking configuration, the proposed architecture has the 38% fewer vertical interconnects for the same throughput and reduces power consumption by 21%. The performances of three-dimensional stacking chips with 64-processor cores are also estimated. As a result, the proposed architecture achieves twenty-times-lower power consumption of inter-chip communications than conventional 2D integration. A uni-directional interconnect configuration and a 3D two-way flow-control protocol were also developed to achieve maximal utilization of the 3D interconnection network. According to simulations using a cycle-accurate stacking LSI model, the proposed technique achieves 90% utilization of the interconnection network, while a conventional design achieves less than 60%.

Elastic shared resource scheduling SOC interconnect architecture for real-time system

We developed an elastic shared resource scheduling SoC interconnect architecture for SoCs that execute various real-time tasks in parallel. It provides both reliability for the hard real-time executions and an optimized overall performance. To meet these requirements, we introduced a hybrid-type scheduling architecture with a static scheduling block for the reliability and a dynamic scheduling block for the efficiency improvement. The dynamic scheduling block taking into consideration the progress of each task makes use of the shared resource utilizations of some tasks that have timing margins for deadlines, and optimizes the overall systems performance. We evaluated the architecture using simple model simulations and benchmarks for multimedia operations. The benchmarks show that the architecture improves the system performance by 23%. This is suitable for consumer-oriented embedded SoCs with severe restrictions on their real-time executions and system costs

Transparent SOC: on-chip analyzing techniques and implementation for embedded processor

An on-chip analysis technique for SOC, which enables system performance to be improved, was developed. The key to this technique is the synchronized analysis of the whole SOC. This is made possible by a circuit structure in which small circuits for analysis are distributed at points on the SOC to be analyzed, and these circuits operate in synchronization through a special network. Benchmarks for multimedia operations (including MPEG encoding) show that this analysis enables us to improve system performance by 17% with minimum trial-and-error. In addition, it was confirmed that the negative impact on chip area when applying this technique is very small. And it is concluded that SOC design time can be shortened during the system-development stage by using this technique.