Jo C. Ebergen

Circuit Techniques to Enable 430Gb/s/mm2 Proximity Communication

Two chips communicate over a capacitively-coupled I/O link at 1.8Gb/s/ch. Channels are placed on a 36mum pitch. 144 channels operate simultaneously for an aggregate bandwidth of 260Gb/s, or 430Gb/s/mm2 in 0.18mum CMOS. Measured energy consumption is 3.0pJ/b and BER is <10-15. Electronic alignment and crosstalk rejection allow reliable I/O for practical implementation

Squaring the FIFO in GasP

This paper presents a method for designing a special type of asynchronous circuits, called GasP circuits, and illustrates the method by a novel design of a low-latency, high-throughput FIFO, called a square FIFO. The design method includes a graphical notation that permits the specification not only of circuit topology but also of the time separation between any two succeeding events. A square FIFO test chip has been fabricated in a 0.35 /spl mu/m CMOS process through MOSIS. Test results show that the square FIFO chip can sustain a maximum throughput of 1.56 giga data items per second for a large range of occupancies.

Transistor sizing: how to control the speed and energy consumption of a circuit

We introduce a simple model for calculating transistor sizes of an asynchronous control circuit. The model builds on the theory of logical effort and relates transistor sizes to the speed and energy consumption of a circuit. We show how to calculate transistor sizes quickly, how to calculate the speed limit of a circuit, and how to compare circuits in terms of energy-versus-speed independent of a process technology. We compare three asynchronous control circuits for a FIFO: a chain of C-elements, an asP control, and a GasP control.

GasP control for domino circuits

We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare favorably with previously published control circuits. We present some results from a chip implementation of several 64-bit domino adders in a TSMC CMOS 180 nm process technology.

New division algorithms by digit recurrence

This paper offers two new division algorithms by digit recurrence. Compared to the standard radix-2 division algorithms with carry-save addition, the new division algorithms trade off a simpler selection logic for more alternatives in the basic repetition step. Our final division algorithm is potentially faster and more energy efficient than radix-2 division with carry-save addition, because the selection logic has less delay and the repetition steps on average perform fewer additions and subtractions.

Multiterabit switch fabrics enabled by proximity communication

This article consists of a collection of slides from the authors conference presentation on multiterabit switch fabrics enabled by proximity communication. Some of the specific topics discussed include: future interconnect needs and requirements; data center trends; the concept of proximity communications; removing the chip input/output bottlenecks; system architectures to support interconnections; switch prototype characteristics; single-stage PxC switch advantages; system design considerations; scalable switch architecture; and future directions for proximity communication.

Notes On Pulse Signaling

This paper reports results of a study on pulse signaling. In pulse signaling, components communicate by means of pulses instead of voltage transitions. The functionality of the components is very similar to the functionality of components used in so-called asynchronous transition signalling. In asynchronous transition signalling, communication events are represented by voltage transitions, whereas in pulse signaling communication events are represented by pulses. We describe various implementations of pulse-signaling components, report on the energy efficiencies of our implementations, and look at some robustness aspects.

An asynchronous high-throughput control circuit for proximity communication

We describe an asynchronous control circuit for interchip communication that enables high throughput proximity communication. The circuit has been fabricated in TSMC 180nm technology and operates over a wide range of coupling capacitances between the chips and over a wide range of supply voltages. At the nominal voltage of 1.8 V and a coupling capacitance of 40fF, this control circuit enables a throughput of 3 Giga token items per second for the data path

A fast and energy-efficient stack

We present some novel hardware implementations of a stack. All designs are clockless, fast, and energy efficient, while occupying modest area. We implemented a 42-place stack chip with a family of GasP circuits, making use of automatic transistor sizing and automatic layout generation. Results from simulations show that the chip will function correctly at speeds of up to 1.6 GHz in a 180 nm TSMC process. The cycle time of our stack chip is about 7 FO4 delays and is independent of the number of data items in the stack and the data width. The energy consumption per stack operation depends on the sequence of stack operations, but grows slowly with the number of data items in the stack.

Circuits Without Clocks: What Makes Them Tick?

Most digital circuits have a global clock that dictates when all circuit components execute their basic computation steps. The clock is a convenience for the designer, because the clock synchronizes all basic computations to its ticks. On the other hand, the clock can be a serious inconvenience with respect to speed, power consumption, modularity of design, and reduced electro-magnetic radiation. A clockless circuit is essentially a distributed system in-the-small, where the main challenge is the coordination of all basic computations in a fast and energy-efficient manner. A growing research community is exploring the benefits of circuits without clocks. In this talk I will give a brief overview of clockless circuits, illustrate their potential by means of some ‘live’ demos, and discuss current challenges.