Iwan Vervoort

Self-annealing characterization of electroplated copper films

Self-annealing of electro-chemically deposited copper films is described and studied, with a focus on the effect of process parameters like concentration of the organic additives, current density or thickness of plated copper. Sheet resistance and stress have been monitored and a non-correlated behavior has been observed for these two film characteristics, indicating that other phenomena than the grain growth typically associated with the room temperature recrystallization are likely to be involved. Diffusion/desorption of carbon containing molecules incorporated in the copper film from the bath additives could be a mechanism for stress release.

Grain Growth, Stress, and Impurities in Electroplated Copper

The widely observed secondary grain growth in electroplated Copper layers is shown to be incomplete after the sheet resistance and stress of the layer appear to have stabilized. Instead the layer is in an intermediate state with a grain size distribution that depends on the plating conditions. Further extensive annealing at high temperatures results in an additional considerable enlargement of the grain structure, accompanied by an additional decrease of the sheet resistance and desorption of impurities that were incorporated during plating.

Two-step room temperature grain growth in electroplated copper

Electroplated copper exhibits some surprising changes at room temperature in sheet resistance, stress, and microstructure. This behavior, now known as self-annealing, is shown here to be intimately linked to the composition of the plating bath and the resulting incorporation of organic additives in the Cu layer. Their addition is a necessary condition for self-annealing to occur, but slows down the process for higher concentrations. The phenomenon also depends critically on film thickness, showing an accelerated transformation when film thickness increases. This dependence is explained in terms of a very rapid primary crystallization from the top surface down just after deposition, followed by a slower lateral recrystallization producing large secondary grains. The stress and sheet resistance during recrystallization are identified as two noncorrelated variables.

Characterisation and integration feasibility of JSR's low-k dielectric LKD-5109

Increasing the circuit density is driving the need for lower permittivity interlayer dielectrics (ILD) to reduce the capacitance between long parallel lines. JSRs LKD-5109, an MSQ-based material, is one of such low-k materials for the 65-nm node. The feasibility of integrating LKD-5109 in a single inlaid structure has been investigated. Thermal stability, chemical compatibility to stripping agents and CMP slurries are verified. A single damascene structure incorporating a dual CVD hard mask has been attempted and electrical results have been evaluated.

Integration of Cu and low- k dielectrics: effect of hard mask and dry etch on electrical performance of damascene structures

Abstract In this work we discuss the importance of selecting the hard mask material and choosing the optimum dry etch and post-CMP clean processes on the integration of Cu and organic low-k dielectrics. The hard mask material plays an important role in the interline capacitance and in the effective dielectric constant of the interconnects. One generation of effective k can be gained simply by replacing the hard mask material by one with a lower dielectric constant, instead of moving to a more advanced low-k material. Interline leakage is not affected by the hard mask material and low values (∼10−9 A/cm2) are obtained at electric fields of 1 MV/cm for structures with spacing down to 0.2 μm. A non-optimized dry etch process for trench definition can result in undercutting, which affects the Cu filling of the trenches. From our results it is clear that the process conditions (lithography, etch, CMP) affect the geometry of the structures, which has a big impact on the effective dielectric constant of the interconnects.

Non-correlated behavior of sheet resistance and stress during self-annealing of electroplated copper

A study of the sheet resistance and stress of electrochemically deposited (ECD) blanket copper layers on a TaN barrier shows that the time dependence of these two parameters are not necessarily the same. This indicates that they are not simply interconnected through the grain size distribution changes occurring at room temperature. The plating bath composition and the resulting contaminant incorporation in the Cu layer during ECD has been identified as an additional important parameter in the explanation of the self-annealing behavior.

Grain structure evolution during annealing of electroplated Copper

The recrystallization of electroplated Copper proceeds in two distinctly different phases. Firstly, secondary grain growth occurs with an activation energy of ∼0.92 eV. Impurities, incorporated in the layer during plating are pushed into the grain boundaries during this process and Carbon then readily diffuses out to the surface. However, Hydrogen and Sulfur are less mobile and accumulate in the boundaries, thereby stabilizing the structure. Only during an extended anneal at elevated temperature is a desorption of these elements observed and does a further grain enlargement commence. This is accompanied by a strong increase in the stress driven (200) volume fraction as a result of grain boundary volume elimination.

Integration feasibility of porous SiLK* semiconductor dielectric

The feasibility of integrating a SiLK* Semiconductor Dielectric film (*trademark of The Dow Chemical Company) that contains closed pores was studied using a single damascene test vehicle. The study focussed on tool qualification, process set-up and single damascene feasibility to demonstrate technology extendibility. The results indicate that only minor changes have to be made to the process conditions when transitioning from a dense to a porous SiLK* film.

Critical issues in the integration of copper and low-k dielectrics

Single and dual damascene Cu/low k processes are evaluated. Critical integration issues are discussed. Good Cu continuity is obtained over long meanders. The via resistance in dual damascene structures is optimized and the values obtained are almost three times lower than those achieved for a conventional Al/W metallization process. The interline capacitance was evaluated for various etch and strip procedures. The effect of the Cu/low k process on a front end of line 0.25 /spl mu/m n-MOS process is investigated. The metallization process does not affect the performance of either transistors or field transistors.

Stress in electrochemically deposited copper

Electroplated copper films exhibit room temperature grain growth and related changes in both sheet-resistance and stress, commonly known as ‘self-annealing.’ While a 20% drop in sheet-resistance has been explained by the growth of large secondary grains forming a percolation path, the changes in stress are not as easily interpreted. Here we show that they are linked to a desorption of compounds that are incorporated in the copper during deposition of the film. The incompleteness of a top-down crystallization just after deposition clarifies the thickness dependence of the stress remaining in the film after self-anneal.