Iwona Turlik

Electroplated solder joints for flip-chip applications

A step-by-step description of a solder electroplating process for flip-chip applications is provided. The necessity of phasing Cr and Cu in the under-bump metallurgy (UBM), which also functions as the current path during plating, is verified by a scanning-electron-microscope (SEM) study of the intermetallics in the reflowed solder joints. Characteristics of the SnPb solder plating bath are presented, and key issues on designing and operating manufacture scale cells are identified. Mathematical modeling of the plating process confirms the capability of the plating process to produce solder bumps of uniform volume and solder composition. Feasibility of the electroplated solder bumping process is demonstrated on dice with an area array of pads of a approximately 0.005-in diameter on a 0.010-in pitch. Data on preliminary mechanical testing conducting to evaluate the integrity of the solder joints are presented. >

A thermal module design for advanced packaging

A hybrid silicon wafer-scale multi-chip packaging design was chosen as the basis for a high performance, high power dissipation vehicle suitable for VLSI/ULSI applications. The package supports 25 chips (l x l cm), each capable of dissipating as much as 40 W. The heat generated by the chips is removed by water channels in the underlying structure. Deep- (about 1000 μm), and shallow- (about 100 μm. deep), channel designs, with a water flow rate of 499 cc/sec, and 39 cc/sec, respectively, have been analyzed. Both designs are capable of keeping circuit temperature rise small, while maintaining a uniform chip temperature. The temperature distribution of the thermal module was obtained by solving the 2-D heat conduction equation for isolated heat sources (the chips), and heat sinks (the water channels). Assuming that each of the 25 chips dissipates 40 W/cm2, and heat is removed only via water flow, the maximum chip tempertaure(tcc which occurs at the center of a chip) rise relative to inlet water temperature is 11.4° C, and 19.0° C for the deep, and shallow designs, respectively. The maximumtcc variation between chips on the module (the same as the water temperature rise), for the cases analyzed, is 0.5° C for the deep-channel design, and 6° C for the shallow-channel design (calculated at 25° C inlet water temperature, and an optimum flow rate). For the extremely-uneven powered case (all chips except one at the inlet end are powered at 40 W/chip), the maximum temperature increases between inlet water temperature and chip temperature,tcc, remain relatively the same, but the maximumtcc variations between chips on the module increase to 11.4° C, and 19° C for the deep, and shallow designs, respectively, as might be expected. The temperature variation on a powered chip is less than 3° C for both the deep- and shallow-channel designs.

Thermal stress analysis of a multichip package design

The authors present a thermal analysis of a thin-film multichip package design, with emphasis on thermally induced stress in the critical package components. The package uses flip-chip solder bonding and thin-film interconnections between chips. Indium was chosen as the die attachment medium between each chip and the water-cooled heat sink. A methodology is given to estimate the stresses in the structure during a power-up. Finite-difference and finite-element computer simulations were used to calculate the temperature and stress distributions under both transient and steady-state conditions. It is shown how thermal gradients, expansion mismatches, and global bending of the structure determine the stress distribution. The components in the module have various thermal time constants, and the stresses during a transient are related to the rate at which each component heats up. For instance, the chips and the heat sink complete 70% of their temperature rise in the first 200 ms, but the substrate takes over 10 s to reach 70% of its steady-state temperature rise. Therefore, even if a design is optimized to be thermal expansion matched under operating conditions, stresses can develop during a transient. >

A high-performance thermal module for computer packaging

A thermal module was designed to transfer heat efficiently from high power dissipation chips to a liquid coolant via forced convection. Turbulent and laminar flow regimes were investigated. Channel geometries for deep channels (1000 μm deep, and used for turbulent flow), and shallow channels (100 μm deep, and used for laminar flow) were optimized for high heat transfer coefficient, ease of fabrication, and better structural rigidity of the module. A 4″ x 4″ module, made out of Cu, was tested using a 4″ Si “thermal” wafer as a heat generating source as well as a temperature sensor. Wafer scale integration and high energy ion implantation were employed to obtain nine l x l cm heat sources, and temperature sensing diodes embedded within the thermal wafer. For the deep channel design, the maximum device temperature rise on the module was 18° C for a power dissipation of 42 W/chip, and a flow rate of 126 cc/sec. For the shallow channel design, the temperature rise was 19° C for a flow rate of 19 cc/sec, and a power dissipation level of 42 W/chip. With all nine chips on the thermal module powered to 42 W/chip, the maximum chip to chip temperature variations were found to be 2 and 8° C for deep and shallow channel designs, respectively.

A review of the skin effect as applied to thin film interconnections

As the rise time of digital pulses is reduced to the subnanosecond range, the skin effect becomes an important issue in high-speed digital systems. The various approaches (theoretical and experimental) which have been taken to study the skin effect are surveyed. Various methods that accommodate the skin effect phenomenon into conductor design rules for high-speed digital systems are examined and compared. The resulting impact of these accommodations on high performance ULSI/VLSI multichip packages is addressed. >

Shear deformation of indium solder joints

Indium solder joint deformation was investigated under conditions of shear loading and stress relaxation at room temperature. The deformation behavior was characterized as a function of strain, strain rate, joint thickness, and hold time. Work hardening during loading was found to increase with strain rate in the range of 10/sup -4/ to 10/sup -2/ s/sup -1/ and decrease with joint thickness in the range of 200-600 mu m. The latter suggests that a thick layer of indium will reduce thermal stresses in die attachment applications. The work hardening behavior was also dependent on the amount of recovery that occurred in the prior stress relaxation cycle. For relaxation times of 2 to 13 h, nearly complete recovery occurs if the plastic strain is less than about 0.02. For shorter relaxation times of larger strains, the material was left in a work hardened state. The stress-strain rate characteristics during relaxation were found to be a function of the initial strain level and the spring constant of the assembly. It was demonstrated how a material constitutive relation can be used with the assembly spring constant to calculate stress reduction with time. This procedure can be applied to any electronic assembly which undergoes stress relaxation during a constant temperature hold.<<ETX>>

Passivation schemes for copper/polymer thin film interconnections used in multichip modules

The use of thin inorganic dielectric films as barrier layers between copper and polyimide was examined. Emphasis was placed on discovering the effectiveness of the barrier layers in preventing copper/polyimide interaction and determining its impact on the high-frequency electrical performance of transmission line structures. The integrity of the inorganic dielectric layers as diffusion barriers for the copper was analyzed using transmission electron microscopy. These effects were studied by depositing thin layers of Si/sub 3/N/sub 4/, SiO/sub 2/, and SiO/sub x/N/sub y/ between chromium/copper/chromium lines and either Dow benzocyclobutene or Dupont 2525 polyimide. Both sputtered Si/sub 3/N/sub 4/ and PECVD SiO/sub x/N/sub y/ behaved as diffusion barriers, which resulted in improved performance at very high frequencies over unprotected transmission lines.<<ETX>>

Simulation and design of lossy transmission lines in a thin-film multichip package

A thin-film multichip package design was evaluated for its applications in packaging high-performance VLSI/ULSI chips. Typical thin-film interconnections (copper lines 8 mu m wide and 4 mu m thick) were analyzed, and a large CMOS driver was used in the simulation. It was found that a pitch of 32 mu m for the microstrip configuration and 20 mu m for the stripline configuration is required to obtain a low-crosstalk environment for an input frequency up to 1 GHz. It is shown that long lines (length between 8 cm and 18 cm) do not need any termination, but short lines (shorter than 8 cm, but longer than the length at which a line is considered to be a lumped circuit) must be terminated with customized termination resistors to obtain optimal package performance. The loading effects n the termination behavior of short and long thin-film microstrips are also discussed. It is shown that high power generation in thin-film lines at a high frequency (1 GHz) would require an advanced cooling technique for the thin-film multichip package. >

Calculation of electrical parameters of a thin-film multichip package

The calculations of the electrical parameters of a thin-film multichip package are presented. It is shown that a commonly used 2-D device simulator, PISCES, can be used to compute the electrical parameters of the thin-film lines up to a frequency where the skin effect is important. For trapezoidal conductor cross-sections, it is shown that the maximum variations of self- and mutual (coupling) capacitances are within 10% of their corresponding rectangular values when the sidewall angle of the conductor is varied up to 30 degrees , and the line cross-section area is kept constant. For the case when the conductor base is kept constant, the variation in mutual capacitance is found to be within 30% and that for self-capacitance is found to be within 12% when the sidewall angle is varied up to 30 degrees . A simple R-L-C circuit is used to represent a three-conductor lossy transmission line system, and SPICE is used to analyze the responses in the time domain. A thin-film multichip package design is briefly outlined. A HP-8510 network analyzer is used to verify the simulation results. >

Cu CVD from Copper(II) Hexafluoroacetylacetonate I . A Cold Wall Reactor Design, Blanket Growth Rate, and Natural Selectivity

An atmospheric pressure cold wall reactor was designed and built for the purpose of studying the thermal decomposition of Cu(hfa) 2 as a repair technique for broken copper interconnection lines, using thermally biased substrates, and a laser to heat localized areas to a temperature appropriate for the deposition of pure copper. In this paper, a discussion of the design is presented, and theoretical and experimental blanket copper deposition growth rates in argon and forming gas are discussed. The primary goals of the present work were the design of the system, the determination of blanket growth rate characteristics, and examination of the tendency for natural selectivity to occur on two contiguous dielectric materials, SiO 2 and polyimide. In studies of natural selectivity, deposition was observed on SiO 2 , but not on contiguous polyimide at substrate temperatures of 340°C down to 270°C or lower, using argon as a carrier/diluent, and from 270°C down to 150°C, using argon/hydrogen mixtures (9 :1) as a carrier/diluent.