Michele Rodrigues

BJT effect analysis in p- and n-SOI MuGFETs with high-k gate dielectrics and TiN metal gate electrode for a 1T-DRAM application

This paper presents an analysis of the bipolar effect in triple-gate n- and p-SOI devices with high-k/TiN metal gate. High-k dielectrics and thicker TiN achieve a larger trigger voltage. However, a reduced program window is found for MuGFETs with high-k dielectrics. p-FET devices give rise to a smaller sense margin and program window due to the reduced hole mobility. Narrow fin devices exhibit a larger trigger voltage and reduced program window and sense margin for a given VDS.

Gate stack influence on GIFBE in nFinFETs

The aim of this work is to study for the first time the gate induced floating body effect (GIFBE) of triple gate nFinFETs devices with different gate stack options for working function (WF) engineering. Based on electrical characterizations it is shown that the presence of a cap layer like Dy2O3 increases EOT and reduces the gate effective WF which decrease VFB and VT. As a consequence the transconductance also decreases and a positive shift of the onset of the GIFBE is observed both at room and at high temperature.

Influence of the Tunneling Gate Current on C-V Curves

This paper presents a study of the tunneling gate current influence on the Capacitance vs. Voltage curve in deep submicrometer CMOS technology. Two-dimensional numerical simulations are performed considering thin gate oxide and N+ polysilicon as a gate material. The influence of the tunneling gate current on the polysilicon depletion region is also analysed. It is observed that the tunneling current masks the polysilicon depletion effect due to the large increase of the substrate silicon depletion region.

Analog parameters of MuGFET devices with different source/drain engineering

This work characterizes the analog performance of SOI n-MuGFETs with different source/drain configurations. Devices without source/drain extension lead to a larger intrinsic voltage gain, even with the reduced transconductance, due to the increased Early voltage. At the same time, they showed a degradation of the interface quality with a larger low-frequency noise and reduced linearity. On the other hand, they can achieve reduced GIDL current due to the suppressed vertical electric field.

Effects of HfSiO nitridation and TiN metal gate thickness on p- and n-SOI MuGFETs for analog applications

An evaluation of the analog performance of p- and nMuGFETs with different TiN metal gate thickness and HfSiO gate dielectrics with and without post-nitridation has been reported. The devices with HfSiON dielectrics showed a lower transconductance and CET, but a higher VT, which is related to an increased VFB. The post-nitridation also reduces the impact of the different TiN thicknesses. A higher intrinsic gain is observed for pFETs with a thinner TiN metal gate and a HfSiO dielectric witch demonstrate overall better analog characteristics.

Impact of the TiN layer thickness on the low-frequency noise and static device performance of n-channel MuGFETs

In this work, the impact of the TiN metal gate electrode with different thickness on the low‐frequency noise of n‐channel MuGFETs is investigated. Thicker TiN metal gate electrodes show a higher threshold voltage VT, with a lower maximum transconductance and low‐field mobility. At the same time, the equivalent capacitance thickness, CET, increases with a subsequent reduction of the gate leakage current. Higher number of TiN deposition cycles also showed an increase in the effective oxide trap traps density (Not). This increase of Not is more related to a larger amount of oxygen incorporated during the deposition of a thicker TiN layer, leading to a higher interfacial oxide layer (IL) thickness, than with the increase of the interface traps.