J. Brett Rolfson

0.35-μm lithography using off-axis illumination

Trends in optical lithography lead to 0.35 micrometers resolution as being the next critical linewidth for semiconductor production. The 64 Mb DRAM technologies will require this. Current i-line lithography techniques lack sufficient production tolerance for 0.35 micrometers . To achieve greater depth of focus and exposure latitude, a number of new techniques are being explored. These include phase shifting masks, multiple focal plane exposures, surface imaging, DUV lithography as well as off-axis illumination. This paper examines the contribution of off-axis illumination towards the improvement of process latitude. Experimental data using 0.54 and 0.48 NA lenses are presented showing the relative advantages and disadvantages of this technique. This data is evaluated for its potential production use for 0.35 micrometers lithography. The effect of off-axis illumination is evaluated for isolated lines, dense lines, sagittal/tangential lines, and contact features. To examine thin film effects, a number of commercially available photoresist processes are used for these tests. In addition, novel solutions to limitations encountered with off-axis illumination are modeled and experimentally verified.

Lithographic performance at sub-300-nm design rules using a high-NA I-line stepper with optimized NA and (sigma) in conjunction with advanced PSM technology

There is growing consensus that 350 nm design rules will be accomplished using i-line lithography. Recent developments in i-line lithography have pushed NA and field size to acceptable levels for 64 MB DRAM manufacturing. Simpler PSM technologies may be used to augment performance in first generation 64 MB DRAM manufacturing. Depending on the topography requirements, it may be necessary to have more process latitude at critical line/space layers. I-line lithography, with conventional binary intensity masks (BIM) should provide adequate process latitude at 400 nm design rules. Incremental improvements in process latitude at feature sizes around this design rule can be obtained using attenuated phase PSM technology. This paper presents data on the implementation of BIM and various PSM technologies in conjunction with a variable NA, variable (sigma) i-line stepper. Optimization of NA and (sigma) have been performed using the various mask technologies to maximize process latitude at features sizes from 450 nm down to below 300 nm. Ultimately, a path is provided to achieve adequate lithographic performance for both first and second generation 64 MB DRAM manufacturing.