M. Koyanagi

Impact of remnant stress/strain and metal contamination in 3D-LSIs with through-Si vias fabricated by wafer thinning and bonding

Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated. The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (µRS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 °C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor.

High-step-coverage Cu-lateral interconnections over 100 µm thick chips on a polymer substrate—an alternative method to wire bonding

We propose a novel chip in the polymer board interconnect method for packaging different kinds of chips on a wafer level, where conventional wire bonding may not be possible due to either space or mechanical constraints. High-step-coverage copper (Cu)-lateral interconnects formed over 100??m thick Si chips by the electroplating method have been investigated for their microstructure and electrical characteristics, using the field emission scanning electron microscope and semiconductor parameter analyzer (Agilent, 4156C). The obtained coverage ratios (i.e. the layer thickness on the chip surface to the sidewall of the chip) for each formed layer, i.e. the tantalum barrier layer, Cu seed layer, SiO2?dielectric layer and electroplated Cu layer, were 3:1, 3:1, 1.5:1 and 1:1, respectively. The measured mean electrical resistances for 36??m???2000??m and 58??m???2000??m interconnect lines were respectively 31.1 and 24?m?, and the difference between measured and calculated resistance values was less than 5%. The good quality of as-fabricated Cu-lateral interconnects was evidenced from the observed low resistance values for isolated interconnects and the linear change in daisy chain resistance with the number of interconnects. More importantly, even at a high operating temperature of 150??C, the resistance value of the Cu-lateral interconnect over the integrated chip was very close to that of the resistance value of interconnect on the plain wafer. The suitability of this technique in integrating various chips heterogeneously was validated from the no observed change in transistor behavior due to this technique. Since this is a CMOS compatible interconnection method between the polymer substrate and chip, it can readily be scaled up to the wafer level.

Ultrafast parallel reconfiguration of 3D-stacked reconfigurable spin logic chip with on-chip SPRAM (SPin-transfer torque RAM)

We have developed novel 3D-stacked reconfigurable spin logic chip having ultrafast on-chip SPRAM to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using 3D integration technology. From the SPRAM cell evaluation, the fastest write speed of 5 ns was obtained in the circuits. To realize higher performance reconfigurable LSIs, parallel reconfiguration was fully demonstrated for the stacked reconfigurable spin logic chips for the first time. Both ultrafast on-chip SPRAM and 3D-stacked structure will open a new era of reconfigurable LSIs.

Electrical evaluation of Cu contamination behavior at the backside surface of a thinned wafer by transient capacitance measurement

The behavior of Cu contamination at the backside surface of a thinned wafer in a three-dimensional (3D) LSI was electrically evaluated by capacitance–time (C–t) analysis. In order to electrically evaluate Cu diffusion characteristics, MOS capacitors were fabricated using the thinned wafer of 50 µm and 100 µm thickness, respectively. For an accelerated Cu diffusion test, a thin Cu layer was deposited at the back surface as a contamination source. Cu atoms were artificially diffused into the substrate by annealing at 200 °C and 300 °C for various times in nitrogen ambient. The C–t curves of a MOS capacitor formed on a 100 µm thickness substrate were degraded even after annealing at 200 °C. It means that Cu atoms diffuse into the active region and reach the Si–SiO2 interface during relatively low-temperature annealing. By increasing time and temperature, the transient time tf is more seriously decreased. The C–t curves of the MOS capacitor formed on the Si substrate of 50 µm thickness were more seriously degraded even after the initial annealing at 200 °C for 5 min. These results indicate that the Cu contamination issue becomes more severe in a thinner Si substrate.This study shows that C–t analysis is a highly promising method to electrically evaluate the influence of Cu contamination on device reliability in the 3D LSI.

Cu lateral interconnects formed between 100-µm-thick self-assembled chips on flexible substrates

A very new interconnection method, namely Cu lateral interconnection is proposed and tested for the heterogeneous multi-chip module integration in which MEMS and LSI chips are self assembled onto the flexible substrate. Here, the lateral interconnects runs between a few hundred microns thick chip and the Si or flexible substrates as well as at inter chip level. These Cu lateral interconnects were fabricated via conventional electroplating technique. As formed single as well as daisy chain lateral interconnects (both are crossing over the thick test chips that are face-up bonded onto the flexible substrates by self-assembly) were characterized for their electrical characteristics. We have obtained a low resistance values for the Cu lateral interconnects which are close to the calculated values. Further, a module contains RF test chips that are interconnected by this unique Cu lateral interconnections has been tested for the operation.

Mechanical characteristics of thin dies/wafers in three-dimensional large-scale integrated systems

Ultra-thin silicon dies/wafers with thickness less than 30 μm are profoundly used in the 3D-integration (vertical stacking of functional chips) and in the optoelectronics, in order to reduce the interconnect length and the resistive-capacitive delay. However, to improve the quality and fabrication yield of the three-dimensional large-scale integration (3D-LSI) process, it is important to have very good mechanical properties of such ultra-thin dies. Mechanical properties of the ultra-thin dies such as Young modulus (using nano-indenter), residual stress (by laser micro-Raman spectroscopy), and also the crystal orientation (by using electron back-scatter diffraction) were investigated with respect to different die thinning processes (chemical mechanical polishing, plasma etching, dry polishing, kai-dry polishing, poly grinding, ultra-poly grinding, #2000, etc), for various wafer thicknesses (10 μm, 30 μm, 50 μm, 100 μm, 200 μm) and for the different kinds of the wafer (P/P+, P/P-, and wafer with internal gettering (IG) layer). The chemically-mechanically polished ultra-thin dies/wafers were found to be extraordinarily good in terms of mechanical strength as well as residual stress as compared to the ultra-thin dies/wafers fabricated by all other die thinning procedures.

A novel atomic doping technology for ultra-shallow junction of SOI-MOSFETs

A novel technology to fabricate an ultra shallow source and drain extension (SDE) junctions for the future SOI-MOSFETs was investigated. In this technology, a dopant in an adsorbed layer on SOI surface diffuses into the substrate by the rapid thermal annealing (RTA) or laser annealing (LA). Arsenic adsorbed layer is formed using UHV CVD apparatus during thermal decomposition of AsH3 on Si (001) at 550 °C with a base pressure of 1× 10 − 10 Torr. RTA and LA have been identified as preferred annealing process for shallow junction formation because it provides low thermal budget control for junctions and high level of dopant activation and defect annealing. This method made it possible to control the junction depth with low sheet resistance for the sub 0.1 m SOI-MOSFET.

Improved C-V, I–V characteristics for co-polymerized organic liner in the Through-Silicon-Via for high frequency applications by post heat treatment

The effect of post-heat treatment of chemical-vapor-deposited polyimide (PI) liner along the Cu-TSV side-wall in the 3D-LSI chips was investigated for leakage current, parasitic capacitance and thermal stability by analyzing current-voltage (I-V), capacitance-voltage (C-V), and x-ray photo-electron spectroscopy (XPS) data. From the I-V data it is inferred that the post heat treatment of 250 nm-thick PI at 200 °C has tremendously suppressed the leak current as compared to the leak current in the pristine PI film. In the case of annealed PI the leak current was minimized to nearly half for the stress voltage of up to ±20 V, whereas it was reduced by nearly three (3) orders for the stress value of ±40 V. The post annealing process also suppresses the hysteresis, and this effect is pronounced for the thicker film.

Locally induced stress in stacked ultrathin Si wafers: XPS and μ-Raman study

Induced local stress arising from local deformation of top silicon die in the vertically stacked LSI die has been investigated via x-ray photoelectron spectroscopy (XPS) and micro-Raman spectroscopy (μRS). The large positive shift in the core level Si-2s and Si-2p XP spectra for the thinned die revealed that thinned dies were under heavy stress/strain even before stacking. The core level binding energy shift, ΔEb for Si-1s core level and the relative chemical shift ΔEr for Si in the vertically integrated die system showed that the stacked Si dies were under different stresses in the μ-bump and the bump-space regions. It was also inferred from the μRS results that the stacked 10 μm-thick-Si dies were under large tensile strain of >;1.5 GPa and a relatively small compressive stress of ~0.5 GPa in the μ-bump and bump-space region, respectively.

Development of self-assembled 3-D integration technology and study of microbump and TSV induced stress in thinned chip/wafer

We have proposed and demonstrated the self-assembly technology that uses liquid surface tension to create a 3-D super-chip. Lots of chips can be simultaneously, precisely, and quickly aligned onto wafers with the self-assembly. We also studied the mechanical stress remained in the thinned Si chip/wafer using 2D micro-Raman spectroscopy. The measurement results pointed out that both metal micorbumps and TSVs induced the compressive and tensile stress in the thinned Si, and they might cause serious problems to 3-D LSIs. It is strongly required to remove the remaining stress in the thinnd Si chip/wafer.