J.C. Eble

Glyphmaker: creating customized visualizations of complex data

Glyphmaker allows nonexpert users to customize their own graphical representations using a simple glyph editor and a point-and-click binding mechanism. In particular, users can create and then alter bindings to visual representations, bring in new data or glyphs with associated bindings, change ranges for bound data, and do these operations interactively. They can also focus on data down to any level of detail, including individual elements, and then isolate or highlight the focused region. These features empower users, letting them employ their specialized domain knowledge to create customized visual representations for further exploration and analysis. For ease of design and use, we built Glyphmaker on top of Iris Explorer, the Silicon Graphics Inc. (SGI) dataflow visualization system. The current version of Glyphmaker has been successfully tested on a materials system simulation. We are planning a series of tests and evaluations by scientists and engineers using real data.<<ETX>>

A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001

GENESYS, a hierarchical tool for exploring future ASIC technology and architecture, is described and employed to project high-performance ASIC power drain and clock frequency, a roadmap for interconnect design, and performance, energy, and area limits.

A physical alpha-power law MOSFET model

A new compact physics-based alpha-power law MOSFET model is introduced to enable projections of low power circuit performance for future generations of technology by linking the simple mathematical expressions of the original Alpha-Power Law Model with their physical origins. The new model, verified by HSPICE simulations and measured data, includes: (1) a subthreshold region of operation for evaluating the on/off current trade-off that becomes a dominant low power design issue as technology scales, (2) the effects of vertical and lateral high field mobility degradation and velocity saturation, and (3) threshold voltage roll-off. Model projections for MOSFET CV/I indicate a 2X-performance opportunity compared to NTRS extrapolations for the 250, 180, and 150 nm generations subject to maximum leakage current estimates of the roadmap. NTRS and model calculations converge at the 70 nm technology generation, which exhibits pronounced on/off current interdependence for low power gigascale integration (GSI).

Impact of extrinsic and intrinsic parameter variations on CMOS system on a chip performance

The yield of high performance CMOS digital circuits is demonstrated to be significantly influenced by the magnitude of critical path delay fluctuations due to both extrinsic and intrinsic parameter variations, as well as the number of critical paths in a system on a chip. To evaluate the impact of these parameter variations, a static CMOS critical path delay distribution is developed and analyzed by employing rigorously derived device and circuit models that enable projections for future technology generations. Increasing the supply voltage and, consequently, power dissipation, the distribution is shifted to satisfy the nominal critical path delay for a desired yield. For the 50 nm technology generation, results indicate supply voltage and power dissipation increases of 14-24% and 31-53%, respectively, for extrinsic parameter standard deviations ranging from (a) 5% for effective channel length and 0% for gate oxide thickness and channel doping concentration to (b) 10% for effective channel length and 5% for gate oxide thickness and channel doping concentration.

Minimum repeater count, size, and energy dissipation for gigascale integration (GSI) interconnects

Optimal repeater insertion in long interconnects is used to minimize the interconnect response time by mitigating the effects of resistance. The use of this scheme in future high clock frequency designs can lead to an alarming number of required repeaters as predicted by a compact expression for the total number of repeaters. Novel design equations, which significantly decrease the number and power dissipation of these drivers, are derived that minimize the repeater number, size, energy dissipation, or energy-delay product.

Exploring microprocessor architectures for gigascale integration

As VLSI advances towards billions of fast transistors on a chip (Gigascale Integration, or GSI), it is becoming clear that interconnect issues will dominate. Conventional uniprocessor architectures, developed in an era when interconnect was largely ignored, may be incompatible with this technology. This paper presents a quantitative exploration of architectural alternatives for gigascale technology. It evaluates a set of candidate architectures in 100 nm technology that span a spectrum of uniprocessor and multiprocessor configurations. Results show that a system composed of a small number of moderately complex processors provides the best performance over a wide range of applications. Designs that include large complex uniprocessors are limited by wire delay, and fall short of parallel systems when even a small amount of explicit parallelism is available (greater than 10% of the workload). Similarly, highly parallel designs with many small processors are restricted in sequential environments with limited parallelism. The only designs capable of maintaining Moores law require extremely parallel workloads.

A first generation generic system simulator (GENESYS) and its relation to the NTRS

The National Technology Roadmap for Semiconductors (NTRS) presents projections and goals for microelectronics over the next fifteen years. A set of physical and empirical models encompassing material, device, circuit, architecture, interconnection, and packaging characteristics that describe microelectronic systems have been captured in the first generation of GENESYS, a GENEric SYstem Simulator. From technology parameters projected in the NTRS, GENESYS predicts maximum clock frequency, physical size, power dissipation, and packaging requirements of an ASIC. The outputs of GENESYS are compared to the on-chip clock frequency, chip size, and maximum power projections of the NTRS for ASICs, and then used both to calibrate GENESYS and to subject the NTRS projections to self-consistency checks.

A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI)

Based on Rents Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. The distribution is then used to describe an optimal architecture for a multilevel wiring network that provides maximum interconnect density and minimum chip size for a ULSI system. In addition, this new distribution has been incorporated into a Generic System Simulator (GENESYS), that projects overall performance of future ULSI systems. Assuming various interconnect materials such as copper, aluminum, silicon dioxide, and low dielectric polymers, GENESYS has been used to examine the effects that each material has on overall performance of ASICs over the next 15 years.