Jung Hwan Yum

Metal oxide RRAM switching mechanism based on conductive filament microscopic properties

By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament features controlling TiN/HfO2/TiN resistive memory operations. The forming process is found to define the filament geometry, which in turn determines the temperature profile and, consequently, the switching characteristics. The findings point to the critical importance of controlling filament dimensions during the forming process (polarity, max current/voltage, etc.).

Effects of barrier layers on device performance of high mobility In0.7Ga0.3As metal-oxide-semiconductor field-effect-transistors

We have applied single InP barrier layer with different thicknesses and InP/In0.52Al0.48As double-barrier layer to In0.7Ga0.3As Al2O3 metal-oxide-semiconductor field-effect-transistors (MOSFETs) and investigated their effects on device performance. In0.7Ga0.3As MOSFETs with 3 nm InP single-barrier attain 22% higher peak effective mobility while devices with 5 nm InP attain 58% higher peak mobility than the ones without barrier. Devices using InP/In0.52Al0.48As double-barrier achieve mobility enhancement at both low-field (68% at peak mobility) and high-field (55%) compared to ones without barrier. High channel mobility of 4729 cm2/V s has been obtained using InP/In0.52Al0.48As barrier and atomic-layer-deposited Al2O3 gate oxide.

Self-aligned n-channel metal-oxide-semiconductor field effect transistor on high-indium-content In0.53Ga0.47As and InP using physical vapor deposition HfO2 and silicon interface passivation layer

In this work, we present the electrical and material characteristics of TaN∕HfO2∕In0.53Ga0.47As and InP substrate metal-oxide-semiconductor capacitors and self-aligned n-channel metal-oxide-semiconductor field effect transistor (n-MOSFET) with physical vapor deposition Si interface passivation layer. Excellent electrical characteristics, thin equivalent oxide thickness (∼1.7nm), and small frequency dispersion (<2%) were obtained. n-channel high-k InGaAs- and InP-MOSFETs with good transistor behavior and good split capacitance-voltage (C-V) characteristics on In0.53Ga0.47As and InP substrates have also been demonstrated.

High performance In0.7Ga0.3As metal-oxide-semiconductor transistors with mobility >4400 cm2/V s using InP barrier layer

We have investigated device performance for In0.7Ga0.3As and In0.53Ga0.47As metal-oxide-semiconductor transistors (MOSFETs) with and without InP barrier layer using atomic layer deposited Al2O3 gate dielectric. InP barrier layer was found to provide higher transconductance for both In0.7Ga0.3As and In0.53Ga0.47As MOSFETs, especially for In0.7Ga0.3As. In0.7Ga0.3As MOSFETs with InP barrier layer show much higher transconductance and lower subthreshold swing than other MOSFETs studied. These In0.7Ga0.3As MOSFETs exhibit high drive current of 98 mA/mm (L=20 μm), subthreshold swing of 106 mV/decade and maximum effective channel mobility of 4402 cm2/V s.

Effects of gate-first and gate-last process on interface quality of In0.53Ga0.47As metal-oxide-semiconductor capacitors using atomic-layer-deposited Al2O3 and HfO2 oxides

We have investigated the effects of gate-first and gate-last process on oxide/InGaAs interface quality using In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOSCAPs) with atomic-layer-deposited (ALD) oxides. Sequence of source/drain activation anneal in the process results in remarkable electrical and physical difference. Applying gate-last process provides significant frequency dispersion reduction and interface trap density reduction for InGaAs MOSCAPs compared to gate-first process. A large amount of In–O, Ga–O, and As–As bonds was observed on InGaAs surface after gate-first process while no detectable interface reaction after gate-last process. Electrical and physical results also show that ALD Al2O3 exhibits better interface quality on InGaAs than HfO2.

Gate oxide scaling down in HfO2-GaAs metal-oxide-semiconductor capacitor using germanium interfacial passivation layer

The primary goal of this work is to investigate the capability of gate oxide scaling down in HfO2-based GaAs metal-oxide-semiconductor capacitor (MOSCAP) using a thin germanium (Ge) interfacial passivation layer (IPL). With HfO2 of 45–50A, an equivalent oxide thickness (EOT) of 8.7A was achieved with a low gate oxide leakage current density (Jg) of (2–4)×10−3A∕cm2 at VG−VFB=1.0V. This is the thinnest EOT thickness ever reported for high-k III-V MOSCAPs. On the other hand, with thicker HfO2 of 100–110A, an EOT of 20–22A with Jg of (2–4)×10−6A∕cm2 at VG−VFB=1.0V was attained. In addition, breakdown voltages of gate oxide and hysteresis characteristics according to different thicknesses of HfO2 were studied. The results indicate that a Ge IPL and thin HfO2 enable excellent gate oxide scaling down in GaAs system.

Inversion-type enhancement-mode HfO2-based GaAs metal-oxide-semiconductor field effect transistors with a thin Ge layer

Using a thin germanium (Ge) interfacial passivation layer (IPL), GaAs HfO2-based inversion-type enhancement-mode metal-oxide-semiconductor field effect transistors (MOSFETs) are realized. The n-channel MOSFETs on semi-insulating GaAs substrate clearly show surface modulation and excellent current control by gate bias. The threshold voltage of ∼0.5V, the transconductance of ∼0.25mS∕mm, the subthreshold swing of ∼130mV/decade, and the drain current of ∼162μA∕mm (normalized to the gate length of 1μm) at Vd=2V and Vg=Vth+2V are obtained. In comparison with previous reports, the dc characteristics of the inversion-type GaAs MOSFETs with a Ge IPL and HfO2 dielectric demonstrate much similar results.

Atomic layer deposited beryllium oxide: Effective passivation layer for III-V metal/oxide/semiconductor devices

Electrical and physical characteristics of the atomic layer deposited beryllium oxide (BeO) grown on the Si and GaAs substrates were evaluated as a barrier/passivation layer in the III-V devices. Compared to Al2O3, BeO exhibits lower interface defect density and hysteresis, and smaller frequency dispersion and leakage current density at the same effective oxide thickness, as well as an excellent self-cleaning effect. These dielectric characteristics combined with its advantageous intrinsic properties, such as high thermal stability, large energy band-gap(10.6 eV), effective diffusion barrier, and low intrinsic structural defects, make BeO an excellent candidate for the interfacial passivation layer applications in the channel III-V devices.

Improved electrical characteristics of TaN/Al2O3/In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors by fluorine incorporation

In this work, a postgate CF4 plasma treatment has been demonstrated on In0.53Ga0.47As channel metal-oxide-semiconductor field-effect transistors. Fluorine (F) has been incorporated into the atomic layer deposited Al2O3 gate dielectric by postgate CF4 plasma treatment. A smaller subthreshold swing and reduced interface trap density has been achieved with F passivation, suggesting a better interface quality. With CF4 plasma treatment, drive current, transconductance and effective channel mobility has been shown to increase by 13.9%, 12.5%, and 29.6%, in comparison to the control devices, respectively.

300mm FinFET results utilizing conformal, damage free, ultra shallow junctions (X j ∼5nm) formed with molecular monolayer doping technique

We demonstrate for the first time, a 20nm FinFET using a new, conformal, and damage-free monolayer doping technique. Unlike conventional ion-implantation, this approach makes use of a dopant-containing precursor to uniformly assemble a monolayer of covalently bonded dopants to enable an ultra-shallow (Xj∼5nm) and abrupt (0.6nm/dec) junction formation around a high aspect ratio fin structure, which overcomes the possible FinFET pitch scaling limitations of traditional doping techniques. FinFETs featuring MLD junctions were successfully demonstrated with good electrostatics control down to a gate length of ∼40nm. With further scaling of the fin width, sub-threshold swing and threshold voltage roll-off can be further improved. This low damage and conformal doping is a promising technique to address key FinFET scaling issues associated with parasitic series resistance and short channel control for the 15nm node and beyond.