Andreas Thiede

ESD-Protected 24 GHz LNA for Radar Applications in SiGe:C Technology

This paper presents an ESD-protected 24 GHz single-stage differential cascode LNA in Infineons B7HF200 SiGe technology. It is designed to fulfill high robustness requirements for industrial or automotive applications. Performance variation of key parameters has been analyzed in measurement over a wide range of temperatures from −25 ◦ C to 125 ◦ C.T he amplifier offers a gain of 12 dB and noise figure of 3. 1d B at the center frequency of 24 GHz. The circuit exhibits high linearity of −8. 7d Bm and −1. 8d Bm input-referred 1dB compression point and IIP3, respectively. The LNA consumes 12. 6m A from a single 3. 3V supply. The ESD hardness has been investigated using a Transmission Line Pulse (TLP) system. The circuit exhibits minimum 1. 3A failure current on the RF pins, which corresponds to HBM protection above 1. 5k V.T he chip size including the pads is 0.32 mm 2 .

Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer

A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead decision feedback equalizer for 80 Gb/s short-reach optical communication systems is presented. On-wafer tests are developed to determine the maximum operating bit rate of the equalizer. Results are also presented for intersymbol interference mitigation at 80 Gb/s for a 20 GHz bandwidth-limited channel. Further improvements on the architecture of the 80 Gb/s equalizer are discussed and used in the design and on-wafer measurement of a 110 Gb/s equalizer. The equalizers are designed in a 0.13 μm SiGe:C BiCMOS technology. The 80 and 110 Gb/s versions dissipate 4 and 5.75 W, respectively and occupy 2 and 2.56 mm2, respectively.

Low power frequency dividers in SiGe:C BiCMOS technology

This paper reports a 71 GHz static and a 103 GHz regenerative dynamic frequency divider fabricated in 0.25 mum SiGe:C HBT technology with fT/fmax200 GHz. The static divider including the buffer works with a 3.5 V single supply voltage and consumes 140 mW with 42 mW for the master-slave flip-flop (FF). The high speed/power ratio makes it attractive for high-frequency wireless communication systems. The dynamic frequency divider operates from 24 GHz to 103 GHz with 5.2 V voltage supply and consumes 195 mW including the buffer with 41 mW for the divider core, and it can be applied at higher frequencies in low power millimeter wave systems

Comparison of 24 GHz receiver front-ends using active and passive mixers in CMOS

This study compares the key parameters of two integrated receiver front-end architectures: low noise amplifier (LNA) with active mixer against LNA with passive mixer. The authors discuss the differences in the performance and their impact on system characteristics for radar applications. A low-IF down-conversion receiver implementation is considered. The results are compared in measurement for two 24 GHz receiver front-end chips realised in a 0.13 mum digital CMOS process. Both circuits have been characterised over automotive temperature range -40 to 125degC. The front-end with an active mixer offers lower LO power dependence and exhibits better temperature stability, whereas the front-end with a passive mixer has the advantage of better input-referred linearity and lower flicker noise.

Extension of Thru de-embedding technique for asymmetrical and differential devices

Accurate radiofrequency (RF) characterisation of on-chip or on-board devices often requires de-embedding to account for parallel and serial parasitics associated with bonding pads and interconnects. It is usually performed by well-known techniques such as Open-Short, Pad-Open-Short or Thru. However, these approaches or alternative techniques employing more standards assume a specific lumped-element model of bonding structures. This reduces de-embedding accuracy at higher frequencies. The Thru de-embedding technique is analysed in this paper and it is shown that under certain conditions de-embedding can be performed without modelling of the internal structure of the thru standard. The possibility to obtain the parameters of an error network by using a single test structure reduces significantly the costs of manufacturing standards and saves the measurement time. Further, an extension of the Thru technique is introduced. It is shown that at the expense of one more measurement, it is possible to characterise the system without additional assumptions. The presented method can be applied, for example, for de-embedding of fixtures with different connectors on either side. Additionally, the extension of Thru technique for de-embedding of differential devices is proposed. The paper verifies the extension for asymmetrical structures by simulation performed using Sonnet electromagnetic field solver in the frequency range 1-40-GHz. Finally, the extension for differential devices is verified by measurement in the frequency range 1-20-GHz and comparison of the results with Open-Short de-embedding technique.

A low power 24 GHz LNA in 0.13 μm CMOS

This paper presents a 24 GHz differential LNA in 0.13 mum CMOS technology. It is based on a combined NMOS/PMOS transconductor allowing DC-current reuse. A gain of 14 dB and a noise figure of 5 dB have been achieved at the center frequency. The circuit exhibits input-referred 1 dB compression point and IIP3 of -14.1 dBm and -1.7 dBm, respectively. Due to implementation of the virtual ground concept high ESD protection is provided at the RF pins without degrading the high-frequency performance. The measured TLP and HBM ESD robustness is 2 A and 2.5 kV, respectively. The LNA consumes only 12 mA from a single 1.5 V supply. The chip size including the pads is 0.23 mm2.

A 20GS/s 8-Bit Current Steering DAC in 0.25μm SiGe BiCMOS Technology

This paper presents the design of an 8-bit 20 GS/s DAC. The DAC is implemented with a modified current steering architecture where unlike the conventional binary weighted architecture a R-2R ladder DAC architecture is used as the LSB sub-DAC. In simulation the 8-bit DAC shows 7.83 ENOB for 9 GHz of input sinusoidal at 20 GHz of sampling rate with the power dissipation of 2.5 W. The measurement results of the 4-bit LSB sub-DAC show that the sub-DAC can work up to 30 GHz with a power dissipation of 455 mW.

Integrated Magnetic Loop Probe in GaAs Technology for Active Near-Field Sensor

This paper reports on design, simulation and measurement of miniature rectangular loops in OMMIC ED02AH GaAs technology. The loops are intended for integration on chip with other active circuitry for near-field scanning of printed circuit boards (PCB) as well as large scale integrated (LSI) circuits. Our target frequency range is from 1 MHz to 3 GHz and is planned to extend up to 10 GHz. Electromagnetic (EM) field simulation results from two simulators as well as on-wafer measurement results are presented. A new rectangular loop structure using the via-hole and backside metallization is proposed.

Miniature Dipole Antenna for Active Near-Field Sensor

In EMC analysis, electromagnetic near-field scanning of printed circuit boards as well as of large scale integrated circuits becomes more and more popular. One approach to measure electromagnetic field distributions with high spatial resolution and sensitivity is the use of miniature active field probes. A small dipole probe on GaAs substrate intended to be integrated with active circuitry is reported in this work. Our target frequency range is from 1MHz to 3GHz and is planned to extend up to 10GHz. The electrical properties of the sensor are investigated by simulations with two software packages and a lumped equivalent circuit is presented. The effect of the GaAs substrate, the load impedance and the trace width of the dipole structure on the sensitivity of the probe is discussed.

A compact low-power 24 GHz transceiver for radar applications in 0.13 µm CMOS

This paper presents a compact low-power transceiver for 24 GHz radar applications integrated in 0.13 μm CMOS technology. The high integration level includes a low-noise amplifier (LNA), two mixers, on-chip quadrature generation, a voltage-controlled oscillator (VCO), a power amplifier (PA) driver and frequency division by four at a record minimal area of 0.7 mm2. The direct-conversion receiver offers a conversion gain of 12 dB and a DSB noise figure of 5.5 dB, whilst the transmitter provides an output power of -3 dBm with a phase noise of -101 dBc/Hz. The circuit consumes only 88 mW from a single 1.5 V supply.