J.F. DeGelormo

Gate-self-aligned p-channel germanium MISFETs

The authors have fabricated the first gate-self-aligned germanium MISFETs and have obtained record transconductance for germanium FETs. The devices fabricated are p-channel, inversion-mode germanium MISFETs. A germanium-oxynitride gate dielectric is used and aluminum gates, serve as the mask for self-aligned source and drain implants. A maximum room-temperature transconductance of 104 mS/mm was measured for a 0.6- mu m gate length. A hole inversion channel mobility of 640 cm/sup 2//V-s was calculated using transconductance and capacitance data from long-channel devices. This large hole channel mobility suggests that germanium may be an attractive candidate for CMOS technology.<<ETX>>

Capacitance–voltage characterization of silicide–GaAs Schottky contacts

Capacitance–voltage carrier concentration profiling has been used to investigate the high temperature stability of refractory metal silicide films on GaAs. This technique is more sensitive to silicide–semiconductor interactions than is forward I–V characterization since tenacious surface Fermi level pinning of GaAs can yield stable diode barrier height and ideality factor measurements even for some cases of gross silicide–semiconductor interaction. Using C–V characterization we have found tungsten silicide film compositions that exhibit excellent high temperature stability on GaAs and have suggested failure mechanisms for other less stable film compositions.

Shallow n+ Junctions in Silicon by Arsenic Gas‐Phase Doping

Shallow arsenic junctions were formed in short processing times using gas-phase rapid thermal diffusion with arsine or tertiarybutylarsine (TBA). A 60 s gas-phase diffusion at 1100 o C using 3.6% arsine in helium at 760 Torr formed 150 nm junctions with a measured sheet resistance of 100 Ω/□. Shallow junctions were also formed with a 12 min diffusion at 900 o C using 10% TBA in argon at 10 Torr. These TBA-formed junctions have arsenic concentration at the silicon surface greater than 1×10 20 atms/cm 3 and a sheet resistance of 244 Ω/□. In addition, TEM cross sections show no process-induced damage at the junction for gas-phase doping

High-speed, low-voltage complementary heterostructure FET circuit technology

A III-V complementary heterostructure FET circuit technology which offers high-speed at low supply voltages has been demonstrated. This circuit technology is based on the vertical integration of p-channel quantum-well FETs with n-channel FETs fabricated in the underlying layers of a single-growth AlGaAs-GaAs structure. Key features of the p-FET heterostructure design and fabrication technology are discussed, and results on the electrical characteristics and the performance of high-speed ring oscillator circuits are presented. Delays of 144 and 59 ps are obtained in 0.8 and 0.5 mu m gate-length circuits at a 1.25 V supply, which are the fastest speeds yet reported for room-temperature complementary heterostructure FET circuits at low supply voltages.<<ETX>>

High-Transconductance Ingaas/Inaias Sisfets

Summary form only given. SISFETs in the InGaAs/InAlAs lattice-matched-to-InP material system with record transconductance have been fabricated. These devices use an InGaAs channel layer grown on an InAlAs buffer layer grown on (and lattice matched to) a semi-insulating InP substrate. Carriers are induced in the undoped channel layer by the action of a doped InGaAs gate layer acting across an undoped InAlAs insulating layer. The device is thus the analog of the GaAs/AlGaAs SISFET (or more broadly the silicon gate MOSFET) but provides the electron transport advantages of InGaAs. In addition, ion implantation and arsine overpressure rapid thermal annealing of shallow implants into InGaAs were studied, and it was found that shallow self-aligning implantation structures can be achieved with much lower resistance than in GaAs. >

Arsenic gas‐phase doping of polysilicon

Polysilicon layers have been doped with high uniform concentrations of arsenic in short processing times using gas‐phase doping. The polysilicon layers were doped at total system pressures from 1 to 760 Torr with arsine or tertiarybutylarsine (TBA) as gas‐phase dopant sources. An arsenic concentration as high as ≳4×1020 atm/cm3 in 100 nm polysilicon layers was measured after a 60 s diffusion in 2.4% arsine in He at 1000u2009°C at 760 Torr. Using tertiarybutylarsine (TBA) at 3 Torr, a sheet resistance of 2.5 kΩ/⧠ was measured in a 100 nm polysilicon layer after 12 min at 900u2009°C. Doping at temperatures as low as 770u2009°C also gave high arsenic concentrations. Finally, a 6 μm deep DRAM trench capacitor was uniformly doped with arsenic to a concentration of 8×1019 atm/cm3 using gas‐phase doping and a two‐step polysilicon deposition process.

High performance refractory gate self-aligned GaAs MESFETs fabricated by arsine ambient rapid thermal annealing

We have applied arsine ambient rapid thermal annealing (RTA) to the fabrication of high-performance refractory gate self-aligned GaAs MESFETs. This has allowed us to take advantage of some of the strong points of rapid thermal annealing for these devices (reduced dopant movement and gate-channel interaction) without the difficulties of capped RTA (decapping problems, cap thermal-mismatch-stress driven dopant movement and gate-channel interaction) or the uncertain As loss characteristics of uncapped or proximity RTA. Using this technique we have fabricated self-aligned 0.8 micron gate length MESFETs with 50 nm epitaxially-grown channels of 2 × 1018/cm3nominal doping with -0.14 V threshold voltage, k-factor as large as 590 mS/V-mm, maximum transconductance over 550 mS/mm, and over 350 mA/mm current drive capability. We have also fabricated fully-ion-implanted devices using arsine ambient annealing for both the channel and self-aligning n+ implant anneals. For29Si 30 KeV channel implants and29Si 40 KV self-aligning implants we have achieved a k-factor as large as 610 mS/V-mm for a gate length of 0.6 micron. This k-factor is the largest reported for a GaAs MESFET (disregarding anomalous values for devices with hole injection and/or carrier multiplication effects).