Craig Ransom

Gate-self-aligned p-channel germanium MISFETs

The authors have fabricated the first gate-self-aligned germanium MISFETs and have obtained record transconductance for germanium FETs. The devices fabricated are p-channel, inversion-mode germanium MISFETs. A germanium-oxynitride gate dielectric is used and aluminum gates, serve as the mask for self-aligned source and drain implants. A maximum room-temperature transconductance of 104 mS/mm was measured for a 0.6- mu m gate length. A hole inversion channel mobility of 640 cm/sup 2//V-s was calculated using transconductance and capacitance data from long-channel devices. This large hole channel mobility suggests that germanium may be an attractive candidate for CMOS technology.<<ETX>>

Shallow n+ Junctions in Silicon by Arsenic Gas‐Phase Doping

Shallow arsenic junctions were formed in short processing times using gas-phase rapid thermal diffusion with arsine or tertiarybutylarsine (TBA). A 60 s gas-phase diffusion at 1100 o C using 3.6% arsine in helium at 760 Torr formed 150 nm junctions with a measured sheet resistance of 100 Ω/□. Shallow junctions were also formed with a 12 min diffusion at 900 o C using 10% TBA in argon at 10 Torr. These TBA-formed junctions have arsenic concentration at the silicon surface greater than 1×10 20 atms/cm 3 and a sheet resistance of 244 Ω/□. In addition, TEM cross sections show no process-induced damage at the junction for gas-phase doping

Arsenic gas‐phase doping of polysilicon

Polysilicon layers have been doped with high uniform concentrations of arsenic in short processing times using gas‐phase doping. The polysilicon layers were doped at total system pressures from 1 to 760 Torr with arsine or tertiarybutylarsine (TBA) as gas‐phase dopant sources. An arsenic concentration as high as ≳4×1020 atm/cm3 in 100 nm polysilicon layers was measured after a 60 s diffusion in 2.4% arsine in He at 1000 °C at 760 Torr. Using tertiarybutylarsine (TBA) at 3 Torr, a sheet resistance of 2.5 kΩ/⧠ was measured in a 100 nm polysilicon layer after 12 min at 900 °C. Doping at temperatures as low as 770 °C also gave high arsenic concentrations. Finally, a 6 μm deep DRAM trench capacitor was uniformly doped with arsenic to a concentration of 8×1019 atm/cm3 using gas‐phase doping and a two‐step polysilicon deposition process.