J. Freijedo

Time Management for Low-Power Design of Digital Systems

The implementation of complex functionality in low-power (LP) nano-CMOS technologies must be carried out in the presence of enhanced susceptibility to PVT (Process, power supply Voltage and Temperature) variations. VT variations are environmental or operation-dependent parametric disturbances. Power constraints (in normal and test mode) are critical, especially for high-performance digital systems. Both dynamic and leakage power induce variable (in time and space) thermal maps across the chip. PVT variations lead to timing variations. These should be accommodated without losing performance. Dynamic, on-line time management becomes necessary. The purpose of this paper is to present a VT-aware time management methodology which leads to improved PVT tolerance, without compromising performance or testability. First, the methodology is presented, highlighting its characteristics and limitations. Its underlying principle is to introduce additional tolerance to VT variations, by time borrowing, dynamically controlling the time of the clock edge trigger driving specific memory cells (referred to as critical memory cells, CME). VT variations are locally sensed, and dynamic delay insertion in the clock signal driving CME is performed, using Dynamic Delay Buffer (DDB) cells. Then, methodology automation, using the proprietary DyDA tool, is explained. The methodology is proved to be efficient, even in the presence of process variations. Finally, it is shown that VT tolerance insertion does not necessarily reduce delay fault detection, as multi-V DD or multi-frequency self-test can be used to recover detection capability.

Aging monitoring with local sensors in FPGA-based designs

In nanoscale FPGAs, variability and aging significantly limit performance. In this paper, a novel aging monitoring methodology for FPGA-based designs to mitigate those effects is proposed. Local sensors are embedded in the configured functionality, monitoring critical paths, at production or during product lifetime. No design freeze (slice and routing locked) is required. When sensors observe a users defined time guardband violation, safe operation is endangered and action can be triggered, either to reduce clock frequency or to increase core VDD. Simulation and experimental results are presented, using Spartan 6 boards and vendor tools. The testbench uses a Data Acquisition (DAQ) system with Triple Modular Redundancy (TMR) architecture and a Built-In Self-Test (BIST) infrastructure. It is shown that local sensors will anticipate system failure. Various devices are also used to analyze sensitivity to process variations.

Design and Validation of Configurable Online Aging Sensors in Nanometer-Scale FPGAs

In current CMOS nanometer technologies, aging effects may appear after relatively short operating times, compared to the expected lifetime of circuits. Therefore, there is an increasing need for on-chip aging monitoring, especially in high-performance, safety critical systems. This paper presents a programmable aging sensor that can be embedded in field-programmable gate array (FPGA)-based designs, using standard resources available in those devices and with minimal impact on the standard FPGA design flow. Given the limited amount of resources required by the sensor, it can be instantiated not only in the critical paths of a circuit, but also in those that may be identified to be more likely affected by aging effects. Experimental results, obtained in circuits of increasing complexity (where several sensors need to be used), are presented and discussed, demonstrating the good performance of the proposed sensor, as well as its low cost in terms of area overhead and power consumption. Results of aging experiments based on the standard US MIL-STD-883 Method 1015.50 “Burn-In Test” are also reported, demonstrating that the effect of aging on the sensor is negligible compared to that on the circuit under test, which is a key point for practical applicability. The proposed approach provides a novel and efficient solution to the specific FPGA design problems in this context, which are different from those addressed in application-specific integrated circuit design.

Performance Failure Prediction Using Built-In Delay Sensors in FPGAs

The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval. The design procedure is described, including the constrained placement of some delay sensors. The proposed technique is particularly useful to monitor parametric Process, supply Voltage and Temperature (PVT) and aging-induced variations. It can be used during product lifetime, as a predictive delay fault detection technique, either to avoid unreliable operation, or to guarantee correct functionality with lower power consumption. The usefulness of the proposed technique is demonstrated with part of the data processor of a complex design for a medical imaging system used in PET-based mammography, configured in a Virtex-4 FPGA device (xc4vfx60-11ff1152).

Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies

In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-faults due to Power-supply disturbances in nanometer technologies. Using a previously proposed VT (power supply Voltage and Temperature)-aware time management methodology, it is shown that nanometer technologies impose the need of fault-tolerance methodologies, although the margins of tolerance or fault-free operations are being reduced as technology scales down. SPICE simulation results with 350nm, 130nm, 90nm, 65nm, 45nm and 32nm CMOS technologies show an increasing dependence of propagation delays on power supply variations, as technology is being scaled down. Monte Carlo simulations show that, even in the presence of process variations, a dynamic delay-fault tolerance methodology can be rewarding even at nanometer scale, although the margins for Power-supply variations are becoming smaller.

Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment

As IC technology scales down, signal integrity issues such as power supply noise and clock skews are becoming one of the major concerns of gigahertz system-on-chip (SoC) design. Considering that one of the most important mechanisms to degrade signal integrity is electromagnetic interference (EMI), this paper analyzes the effectiveness of a clock duty-cycle (CDC) modulation technique to enhance SoC signal integrity with respect to power/ground voltage transients induced by EMI. The technique is based on a clock stretching logic (CSL) block, which monitors abnormal power grid activity and increases CDC accordingly. Practical experiments based on the implementation of a 32-bit soft-core pipeline processor in an FPGA IC were performed and illustrate the circuit robustness enhancement to power line fluctuations while maintaining at-speed clock rate. These experiments were conducted according to the IEC 62.132-2. Normative for measurement of radiated electromagnetic immunity (TEM-cell method).

Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits

The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology is reviewed, highlighting its characteristics and limitations. The underlying principle is to introduce on-line additional tolerance, by dynamically controlling the time of the clock edge trigger driving specific memory cells. Second, it is shown that the proposed methodology is still useful in the presence of process variations. Third, discussion and preliminary results on the automatic selection (at gate level) of critical FF for which DDB insertion should take place are presented. Finally, it is shown that parametric delay tolerance insertion does not necessarily reduce delay fault detection, as multi-vdd or multi-frequency self-test can be used to recover detection capability.

Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects

In current nanometer technologies, aging effects (due for instance to Negative Bias Thermal Instability) may appear after relatively short operating times, compared to the expected lifetime of circuits, even for relatively short-cycle consumer electronics. Therefore, there is an increasing need for on-chip aging monitoring. This paper presents a programmable aging sensor that can be embedded in FPGA-based designs, using standard resources available in those devices. The sensing principle is to monitor performance degradation over time. Depending on whether dynamic or static aging effects are dominant, the sensor can operate continuously or be only activated at some time intervals. Given the reduced amount of resources required by the sensor, it can be instantiated not only in the critical paths of a circuit, but also in those that may be identified to be more likely affected by aging affects. Experimental results are presented to demonstrate the performance of the proposed sensor.

Robust solution for synchronous communication among multi clock domains

The purpose of this paper is to present a new robust methodology for synchronous communications in a BUS, connecting multi-clock domains. Traditionally, when robust solutions are needed, an asynchronous communication is used. However, the low transfer rates associated with asynchronous solutions make them inadequate for high performance digital systems. On the other hand, synchronous communications do not guarantee dependability for all data, especially when different clock domains are interconnected. In this paper we propose to take advantage of these approaches, by combining, the robustness of asynchronous communication and the speed and simplicity of synchronous communications. A structure has been developed to implement the proposed communication approach. A test chip has been designed to implement that structure and prove the concept. The usefulness of the methodology is demonstrated in a complex FPGA data acquisition system. Simulation results are presented.

Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems

The implementation of complex, high-performance functionalities in low-power nano-CMOS technologies faces significant design and test challenges related to the increased susceptibility to environmental or operation-dependent disturbances, process variations or emerging defect types. This paper describes the application of semi-empirical propagation delay variation models to support the design and test of low-power nanometer digital circuits, taking into account these challenging issues. Results are presented demonstrating that the models provide designers and test engineers with a powerful tool to analytically account for all effects leading to delay faults. They can be used to define parametric delay tests, as well as to design circuits with increased robustness to delay faults under low-power operation. Its derivation and application can be easily automated, allowing them to be integrated in standard flows.