J. Gelpey

An Overview of ms Annealing for Deep Sub-Micron Activation

Millisecond annealing (MSA) has been developed over the last several years as a viable approach to achieve the high electrical activation, limited diffusion and high abruptness needed for junctions in the sub-65nm regime. This paper will provide an overview of the technology including the motivation, technology and some process results. Both main approaches for MSA, sub-melt laser and flash lamp annealing will be discussed as well as the potential challenges to bring these technologies into mainstream manufacturing.

Ultra-shallow junction formation using flash annealing and advanced doping techniques

As the demand for ever shallower, highly active and abrupt junctions continues, it is important to look at both the doping and activation portions of junction formation as a unit process. Advanced doping is useless without annealing methods that limit diffusion and provide high levels of electrical activation and new annealing techniques cannot make the junctions shallower than the as-doped profiles. This work has looked at optimizing several types of advanced doping (Plasma Doping and beamline ion implantation of molecular dopants) and a flash lamp-based ms annealing approach. With this combination, very shallow, abrupt and low resistivity junctions can be formed. Careful characterization was used to ensure the accuracy of the sheet resistance and junction depth measurements.

Experimental and theoretical results of dopant activation by a combination of spike and flash annealing

The diffusion length of the flash anneal is lowest for all different implant conditions. For the arsenic implant similar diffusion length is seen for all the processes that include a spike anneal due to the fact that the overall thermal budget is mainly determined by the spike anneal. Boron implants into crystalline as well as pre-amorphized silicon show similarly low sheet resistance independent of whether they are annealed with spike + flash, flash or flash + spike. For the arsenic implant by far the lowest sheet resistance is seen with a combination of spike + flash anneal. For the boron and arsenic implants the defect density after the flash anneal and the spike + flash anneal is below the weak beam dark field detection limit of the transmission electron microscope therefore suggesting low leakage due to defects present. From the simulations of the arsenic and the boron concentration profiles it can be learned that the spike profile determines the position of the chemical profile and the activation is increased by the subsequent diffusion-less flash anneal. Thus junction depth can be easily adjusted by the spike anneal condition in a spike + flash scheme, while still maintaining a high degree of dopant activation. This offers great flexibility to next generation junction formation. Although in this study the spike and flash annealing were performed in different tools, a combination of spike + flash can be easily run in the Mattson fRTPtrade system. The combination of spike + flash anneals also has been shown to improve the transistor drive current significantly without undesirable shifts in the other transistor characteristics.

Advanced Activation and Deactivation of Arsenic-Implanted Ultra-Shallow Junctions using Flash and Spike + Flash Annealing

Millisecond annealing as an equipment technology provides ultra-sharp temperature peaks which favours dopant activation but nearly eliminates dopant diffusion to form extremely shallow highly electrically-activated junctions. On arsenic beamline implanted wafers the formation of ultra-shallow junctions at peak temperatures ranging from 1275degC to 1325degC was investigated. The thermal stability of these junctions was evaluated by subsequent thermal anneals ranging from 250 degC to 1050 degC with times ranging from seconds up to several hundred seconds. From these data the deactivation/reactivation mechanism for subsequent annealing can be quantified. Furthermore, the combination of spike and flash annealing is investigated to achieve a desired level of dopant diffusion and activation. For arsenic by far the lowest sheet resistance number is achieved by this annealing strategy. Finally, the arsenic profiles are compared to predictive simulation results which address the diffusion and activation at extrinsic concentrations.

Millisecond annealing of high-performance SiGe HBTs

This work reports on first experiments with millisecond flash anneals for SiGe HBTs. Model experiments on blanket wafers were used to study the effects of flash annealing on HBT-typical doping profiles in comparison to the standard spike annealing, and to find out an appropriate temperature range for transistor functionality. An integration lot was processed and analyzed to get a comprehensive insight into the capability of the flash anneal for SiGe HBT fabrication. Parameters of sheet resistances as well as static and dynamic transistor characteristics demonstrate the potential of this technique for the high-speed operation of SiGe HBTs.

Optimization of diffusion, activation and damage annealing in millisecond annealing

Advances in CMOS technology require continuous reductions in the thermal budget employed for activating ion implanted dopants. However, low thermal budget annealing approaches, such as millisecond annealing, must also remove implant damage to minimize junction leakage. This paper explores the trade-offs between dopant diffusion, electrical activation and damage annealing for ultra-shallow junctions (USJ) formed by low energy B implants into both crystalline and pre-amorphized silicon. The study also addressed how low-thermal budget annealing affects the use of strong halo-style doping from As implants. Several annealing methods were studied, with the main focus on flash-assisted RTP™ (fRTP™) at temperatures between 1250°C and 1350°C. Activation was assessed with RsL™ non-contact measurements and Hg-probe four point-probe sheet resistance measurements, as well as a continuous anodic oxidation technique for depth profiling of carrier concentrations and mobility. Residual damage was assessed by photoluminescence, thermal wave studies, optical reflectance and RsL junction leakage current measurements. fRTP effectively activates high-dose, low-energy B implants, while limiting the diffusion to a few nm of profile movement. The limited thermal budget of millisecond annealing reduces, but does not fully eliminate, implant damage from heavy ions implanted at high energy, although very high process temperatures, e.g. ∼1300°C, are more effective in this regard. Strong halo doping greatly increases the junction leakage and for future device nodes it will be important to reduce implantation damage from both USJ and halo implants. Non-invasive damage metrology can help rapid optimization of implantation and annealing conditions. Such measurements will be even more useful when quantitative models can accurately link them to doping and damage profiles.

Process-Induced Diffusion Phenomena in Advanced CMOS Technologies

The continuous scaling of electron devices places strong demands on device design and simulation. The currently prevailing bulk transistors as well as future designs based on thin silicon layers all require a tight control of the dopant distribution. For process simulation, especially the correct prediction of boron diffusion and activation was always a problem. The paper describes the model developed for boron implanted into crystalline silicon and shows applications to hot-shield annealing and flash-assisted rapid thermal processing.

Engineering ultra-shallow junctions using fRTP/sup TM/

This paper discusses engineering of ultra-shallow junctions using a new annealing technique called Flash-assist RTP/sup TM/ (fRTP). This technique offers effective process times in the 1-10 ms range, which fills the gap between traditional RTP and laser thermal processing. A discussion on the evolution of RTP based on the thermal response time of the heat source and wafer is presented. Technical innovations required for fRTP are discussed including why an extremely powerful flash lamp is essential for this application. Comparisons of the various annealing techniques are made and results presented to show the impact on junction depth, abruptness and resistivity. It is shown that a process engineer can more or less independently control diffusion and activation over a wide range enabling the formation of junctions meeting future requirements of the ITRS.

Sub-20 nm abrupt USJ formation with long ms-flash with sub-2 nm dopant motion control

A new combination of long millisecond (1–2.5 ms) flash anneal at high peak temperature(1200–1300°C) and a new absorber with low deposition temperature (<400 C) have been developed to generate highly activated (Rs~ 500 ohm/sq), sub-20 nm abrupt (≤ 3 nm/decade) N+ and P+ junction. This new approach also provides sub-2nm N+ and P+ junction dopant motion control with multiple long ms-flash which are required for precision device centering and doping for 22 nm and beyond devices. High performance SOI CMOS had been achieved with single long ms-flash and matched well with CMOS created with spike RTA+laser. In addition, long ms-flash NFETs was found to need only ~ ½ of the B halo dose and exhibit no anomalous corner leakage which is sometime found in spike RTA+laser NFETs. These results demonstrate better B halo localization in NFETs with long ms-flash.

Process models for advanced annealing schemes and their use in device simulation

In industrial environments, technology computer-aided design is used intensively for the design and optimization of new device architectures. To maintain its usefulness for future technology nodes, process simulation has to be able to predict the activation and distribution of dopants after advanced implantation and annealing schemes. Such annealing strategies will be based either on millisecond annealing at high temperatures or solid-phase epitaxial regrowth. In our contribution we will discuss diffusion and activation models for boron and arsenic. The models were calibrated for a wide range of annealing conditions, ranging from low-temperature annealing up to millisecond flash annealing. Special emphasis is given on their implementation into Sentaurus Process and on their application for the simulation of advanced device architectures.