Wilfried Lerch

The Effects of Small Concentrations of Oxygen in RTP Annealing of Low Energy Boron, BF 2 and Arsenic Ion Implants

Ion implants of 1.0 keV 11 B + , 5 keV BF 2 + , and 2.0 keV As + at a dose of IeI5/cm 2 were rapid thermal annealed (RTA) in a STEAG AST-2800µ with varying percents of oxygen in N 2 , ranging from 0-lppm to 50,000 ppm to investigate the effects of low concentrations of oxygen during anneal. Sheet resistance (R s ), ellipsometry, SIMS, Tapered Groove Profilometry (TGP), and Scanning Force Microscopy (SFM) were employed to characterize these layers. For each of these implant cases, an optimal RTA condition is established which maximizes retained dose while still producing shallow junctions. As a function of O 2 content, anneal temperature and implant condition, three regimes are observed that affect after anneal retained dose. These regimes are: dopant loss to the ambient resulting from etching of Si, dopant loss by out-diffusion from evaporation/chemical reactions, a capping regime that minimizes out-diffusion. In this later regime the dopant loss results from consumption into the RTA grown oxide. In addition, this paper also discusses oxidation enhanced diffusion (OED) and identifies its extent as a function of temperature and O 2 content of the anneal for the three implant conditions investigated. For example, a 1.0 keV 11 B + wafer annealed at 1050°C lOs in a controlled 33 ppm of O 2 in N 2 yields a SIMS junction depth 320 A shallower than previously reported by others.

Boron Ultrashallow Junction Formation in Silicon by Low‐Energy Implantation and Rapid Thermal Annealing in Inert and Oxidizing Ambient

For the formation of ultrashallow junctions, a controlled gaseous ambient during rapid thermal annealing is indispensible. To understand the diffusion/activation mechanism, the influencing and depending variables have to be clarified precisely. Ion implantations of I keV boron at a fluence of Φ 1 X 10 15 cm -2 are annealed isothermally for 10 s at 1000, 1050, and 1100°C in an AST2800∈ rapid thermal processing system under controlled concentrations of oxygen in nitrogen ambient (0-1 ppm up to 1%). The concentration-depth profiles, measured by secondary ion mass spectroscopy, are analyzed within the framework of the kick-out model involving diffusion enhancement via supersaturation of silicon self-interstitials and the Fermi-level effect. The validity of this interpretation is supported by the simulated results which are in good agreement with experimental data. Two input parameters for the SSUPREM IV simulator yield finite values of silicon self-interstitial supersaturation as a function of temperature and oxygen concentrations, values for the boron diffusion coefficient via neutral and positively charged silicon self-interstitials, and data for transient enhanced diffusion. After rapid thermal annealing for 10 s at 1050°C, the junctions vary within 800-1400 A depending on the annealing ambient.

Wet rapid thermal oxidation of silicon with a pyrogenic system

Abstract A pyrogenic steam generator is implemented in a conventional AST SHS2800e RTP system to produce H2O gas ambient for oxide growth enhancement in a Wet Rapid Thermal Oxidation process (WRTO). For similar thermal budgets of wet and dry oxidation, the growth rate is several times higher for the wet process. The temperature sensitivity (unit: A/K) of the process changes strongly with the grown oxide thickness. The influence of H2O:O2 proportion in the process gas on final oxide thickness is also determined and leads to a definition of a `wet process. Isothermal and isochronal thickness data are summarized for the wet oxidation process. All results are analysed with the theoretical growth model of Deal and Grove [1] and compared to previous results with conventional furnace technology. Electrical breakdown properties of the various oxides grown on epitaxial wafers with an average thickness of 140 A are presented.

Crystal Damage Removal by Spike and Flash Annealing

The formation of extended defects resulting from the precipitation of the large amounts of interstitials and vacancies generated during the dopant and pre-amorphisation implantation is the major issue related to the formation of highly doped p+/n junctions. Interactions between defects and implanted dopants produce diffusion and activation anomalies that are among the major obstacles to the realisation of ultra- shallow junctions satisfying the ITRS requirements. The ideal thermal treatment should remove all the damage and get a high dopant activation with minimal diffusion. Modifying first the depth of the end-of-range damage by varying the pre- amorphisation implantation energy and the thermal budget by using second (spike) and millisecond (fRTP) annealing, the optimal values for implantation energy and thermal budget can be extracted for a complete defect annihilation. Transmission electron microscopy is used to determine the crystal quality.

Simulation of Rapid Thermal Annealed Boron Ultra-Shallow Junctions in Inert and Oxidizing Ambient

Rapid Thermal Annealing (RTA) is indispensable for the formation of ultra-shallow source/drain junctions. To improve the annealing conditions, a fundamental understanding of the influences on the diffusion/activation process is necessary. Ion implantations of 1 keV boron at a dose of Φ≈1 I.10 15 cm -2 are annealed in a SHS2800E RTP-system under controlled concentrations of oxygen in nitrogen ambient (0-1 ppm up to 1%). Concentration-depth profiles, measured by Secondary Ion Mass Spectroscopy (SIMS), are simulated within the framework of the kickout model involving diffusion enhancement via supersaturation of silicon self-interstitials. The validity of this interpretation is supported by the simulated results which are in good agreement with expenimental data. After RTA for 10 s at 1050°C the junctions are varying within a range of 800A to 1400Adepending on the annealing ambient. The results of the simulation yield finite values of self-interstitial supersaturation as a function of the oxygen concentration.

Temperature measurement of wafers with varying multilayer structures during rapid thermal annealing

Rapid thermal processing for advanced semiconductor production demands improved temperature and uniformity control because the optical properties of the dielectric layers deposited on the wafer front- and backside strongly influence the temperature measurement. The measurement of temperature gets more and more important because the semiconductor fabs do not stay with only one product. In recent years, the diversity in product and technology has increased within many semiconductor fabrication plants. As a result, there can be large differences in substrate film stacks between wafers for any rapid thermal annealing step. This variety in products and consequently the differences in emissivity have to be controlled with a precise, simple temperature measurement. One possible solution is the PinTC/sup TM/ presented here. This is a low-cost, thermocouple-based alternative to classical pyrometric temperature measurement and works in closed-loop control. The PinTC/sup TM/ is in contact with the wafer backside and almost emissivity independent. It was found that the optical properties of the wafer backside influence the temperature slightly. To show the improvement in temperature measurement this technology is compared to open-loop processing on wafers with different layer stacks on the backside. The absorptivity of the coatings dominate the direct contact measurement. For the various backside coatings power absorption by the wafer element per unit time and emissivity calculations are performed to understand and explain the experiments. Nevertheless, this direct contact temperature measurement technology is reliable for wafer production in closed-loop control or as a secondary temperature monitor. Furthermore, the PinTC/sup TM/ offers good repeatability in the production environment.

New methods of metrology data analysis during semiconductor processing and application to rapid thermal processing

Abstract New mathematical methods for data analysis are presented in this paper. These methods are applied to data derived by semiconductor metrology tools. Sheet resistance data of implant anneal processes on 200 mm wafers done in a rapid thermal processing system are analysed for implanter and RTP tool inhomogeneities. The first method, a separation method, is used to visualise uniformity of semiconductor process equipment (e.g. rapid thermal processors). The second method, also a separation method, is used to analyse input or preprocess uniformity of process-influencing parameters on the wafer (e.g. ion implant systems). Furthermore a subtraction method is shown which provides some additional advantages. Basis for the data processing is a standardised interface developed to import and analyse data files from different metrology equipment such as ellipsometers and four point probes.

Carrier Density Profiling of Ultra-Shallow Junction Layers Through Corrected C-V Plotting

The aim of this report is to present and justify a new approach for carrier density profiling in ultra-shallow junction (USJ) layer. This new approach is based on a capacitance measurement model, which takes series impedance, shunt resistance and the presence of a boron skin on the USJ layer into account. It allows us to extract the depletion layer capacitances in the USJ layer from C-V plotting more accurately and hence to obtain better carrier density profiles. Based on this new approach the carrier density profiles of different USJ layers with and without halo-style implants are obtained and discussed.

New Approaches for Characterization of Advanced Annealing Techniques for Ultra‐Shallow Junction Formation

Low thermal budget annealing approaches, such as millisecond annealing or solid‐phase epitaxy (SPE), can electrically activate ultra‐shallow junctions (USJ) without excessive diffusion, but they must also remove implant damage to minimize junction leakage. This paper presents results from annealing low‐energy B implants into both crystalline and pre‐amorphized silicon. Some wafers also received As implants for halo‐style doping, and some halo‐implanted wafers were pre‐annealed at 1050u2009°C before B‐doping. The final anneal was either SPE at 650u2009°C, spike annealing at 1050u2009°C, or millisecond annealing with flash‐assisted RTP™ (fRTP™) at temperatures between 1250u2009°C and 1350u2009°C. Electrical activation was assessed by sheet resistance (Rs) measurements with conventional four‐point probing (4PP) as well as Hg‐probe 4PP and a non‐contact method. Residual damage was characterized by photoluminescence, thermal wave studies, optical reflectance and non‐contact junction leakage current measurements. Damage from the h...

Radiation Thermometry—Sources of Uncertainty During Contactless Temperature Measurement

Short Time Annealing on a microsecond to nanosecond scale presents new challenges to temperature measurement. Pyrometers are widely used owing to their commercial availability, short response time, easy handling and contactless operation. However, they hold a source for considerable measurement errors. False readings are easily gained producing large errors during temperature measurement.