J. J. Gu

Observation of quantum-Hall effect in gated epitaxial graphene grown on SiC (0001)

Epitaxial graphene films examined were formed on the Si-face of semi-insulating 4H-SiC substrates by a high temperature sublimation process. A high-k gate stack on the epitaxial graphene was realized by inserting a fully oxidized nanometer thin aluminum film as a seeding layer, followed by an atomic-layer deposition process. The electrical properties of epitaxial graphene films are retained after gate stack formation without significant degradation. At low temperatures, the quantum-Hall effect in Hall resistance is observed along with pronounced Shubnikov–de Haas oscillations in diagonal magnetoresistance of gated epitaxial graphene on SiC (0001).

Effects of (NH4)2S passivation on the off-state performance of 3-dimensional InGaAs metal-oxide-semiconductor field-effect transistors

Planar and 3-dimensional (3D) buried-channel InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) have been experimentally demonstrated at deep-submicron gate lengths. The effect of (NH4)2 S passivation with different concentrations (20%, 10%, or 5%) on the off-state performance of these devices has been systematically studied. 10% (NH4)2 S treatment is found to yield the optimized high-k/InP barrier layer interface property, resulting in a minimum subthreshold swing (SS) lower than 100 mV/dec. Moreover, the 3D device structure greatly improves the off-state performance and facilitates enhancement-mode operation. A scaling metrics study has been carried out for 10% (NH4)2 S treated 3D devices with gate lengths down to 100 nm. With the optimized interface passivation, 3D III-V MOSFETs are very promising for future high-speed low-power logic applications.

First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching

The first well-behaved inversion-mode InGaAs FinFET with gate length down to 100 nm with ALD Al2O3 as gate dielectric has been demonstrated. Using a damage-free sidewall etching method, FinFETs with Lch down to 100 nm and WFin down to 40 nm are fabricated and characterized. In contrast to the severe short-channel effect (SCE) of the planar InGaAs MOSFETs at similar gate lengths, FinFETs have much better electro-static control and show improved S.S., DIBL and VT roll-off and less degradation at elevated temperatures. The SCE of III-V MOSFETs is greatly improved by the 3D structure design. The more accurate Dit estimation from the S.S. is also presented.

Size-dependent Transport Study of In0.53Ga0.47As Gate-all-around Nanowire MOSFETs: Impact of Quantum Confinement and Volume Inversion

InGaAs gate-all-around nanowire MOSFETs with channel length down to 50 nm have been experimentally demonstrated by a top-down approach. The nanowire size-dependent transport properties have been systematically investigated. It is found that reducing nanowire dimension leads to higher on-current, transconductance, and effective mobility due to stronger quantum confinement and the volume-inversion effect. TCAD quantum mechanical simulation has been carried out to study the inversion charge distribution inside the nanowires. Volume-inversion effect appears at a larger dimension for InGaAs nanowire MOSFET than its Si counterpart.

Size-Dependent-Transport Study of

InGaAs gate-all-around nanowire MOSFETs with channel length down to 50 nm have been experimentally demonstrated by a top-down approach. The nanowire size-dependent transport properties have been systematically investigated. It is found that reducing nanowire dimension leads to higher on-current, transconductance, and effective mobility due to stronger quantum confinement and the volume-inversion effect. TCAD quantum mechanical simulation has been carried out to study the inversion charge distribution inside the nanowires. Volume-inversion effect appears at a larger dimension for InGaAs nanowire MOSFET than its Si counterpart.

\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}

III-V-on-nothing (III-VON) metal-oxide-semiconductor field-effect transistors (MOSFETs) are experimentally demonstrated with In0.53Ga0.47As as channel and atomic layer deposited Al2O3 as gate dielectric. A hydrochloric acid based release process has been developed to create an air gap beneath the InGaAs channel layer, forming the nanowire channel with width down to 40 nm. III-VON MOSFETs with channel lengths down to 50 nm are fabricated and show promising improvement in drain-induced barrier lowering, due to suppressed short-channel effects. The top-down processing technique provides a viable pathway towards fully gate-all-around III-V MOSFETs.

Gate-All-Around Nanowire MOSFETs: Impact of Quantum Confinement and Volume Inversion

Enhancement-mode p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) on germanium-on-insulator substrate is fabricated with atomic-layer-deposited (ALD) LaLuO3 as gate dielectric. Significant improvement in both on-state current and effective hole mobility has been observed for devices with thermal GeO2 passivation. The negative threshold voltage (VT) shift in devices with GeO2 interfacial layer (IL) further demonstrates the effectiveness of surface passivation. Results from low temperature mobility characterization show that phonon scattering is the dominant scattering mechanism at a large inversion charge, indicating good interface quality. The combination of higher-k LaLuO3 and ultrathin GeO2 IL is a promising solution to the tradeoff between the aggressive equivalent oxide thickness scaling and good interface quality.

III-V-on-nothing metal-oxide-semiconductor field-effect transistors enabled by top-down nanowire release process: Experiment and simulation

In this paper, we have experimentally demonstrated, for the first time, III-V 4D transistors with vertically stacked InGaAs nanowire (NW) channels and gate-all-around (GAA) architecture. Novel process technology enabling the transition from 3D to 4D structure has been developed and summarized. The successful fabrication of InGaAs lateral and vertical NW arrays has led to 4× increase in MOSFET drive current. The top-down technology developed in this paper has opened a viable pathway towards future low-power logic and RF transistors with high-density III-V NWs.

High performance atomic-layer-deposited LaLuO3/Ge-on-insulator p-channel metal-oxide-semiconductor field-effect transistor with thermally grown GeO2 as interfacial passivation layer

With increasing demands for electrostatic control as scaling continues in todays transistors, low dimensional structures continue to gain attention as a pathway for future device scaling because they offer excellent electrostatic control while remaining compatible with straightforward lithography techniques. In particular, MoS2 has attracted interest for transistor applications because its large band gap allows for field effect devices with low off-current, unlike graphene [1]. One key bottleneck, however, is the realization of ohmic contacts on MoS2 to improve FET device on-state performance. With this in mind, we evaluate Ni and Pd contacts on MoS2 as potential alternatives to the already realized Au-MoS2 and Ti-MoS2 contacts [1]. Back-gated transfer length method (TLM) structures with Au, Ni, and Pd contact metals were fabricated on exfoliated MoS2 flakes, with 300nm SiO2 on degenerately doped Si as the substrate. The data indicate that Ni, like Au, makes an ohmic contact to the n-doped MoS2 while the Pd metal contact shows Schottky behavior.

III-V gate-all-around nanowire MOSFET process technology: From 3D to 4D

Recently, encouraging progress has been made on surface-channel inversion-mode In-rich InGaAs NMOSFETs with superior drive current, high transconductance and minuscule gate leakage, using atomic layer deposited (ALD) high-k dielectrics. Although gate-last process is favorable for high-k/III–V integration, high-speed logic devices require a self-aligned gate-first process for reducing the parasitic resistance and overlap capacitance. On the other hand, a gate-first process usually requires higher thermal budget and may degrade the III–V device performance. In this paper, we systematically investigate the thermal budget of gate-last and gate-first process for deep-submicron InGaAs MOSFETs. We conclude that the thermal instability of (NH4)2S as the pretreatment before ALD gate dielectric formation leads to the potential failure of enhancement-mode operation and deteriorates interface quality in the gate-first process. We thus report on the detailed study of scaling metrics of deep-submicron self-aligned InGa...