J. Kao

A DDFS Driven Mixing-DAC with Image and Harmonic Rejection Capabilities

The proposed DDFS-driven mixing-DAC consists of several parallel-connected Gilbert cells driven directly by the binary and thermometer DDFS data compromise between power-dissipation and harmonic-rejection performance is achieved with 5b binary LSBs and 5b thermometer MSBs segmented mixing-DAC. The 2.8-to-3.2 GHz DDFS sampling frequency is selected such that it provides in excess of two samples per cycle up to 1 GHz, while the LO sampling spurs (fsplusmnfL0) are always outside the receiver desired frequency band. It is dynamically adjusted for each received channel to minimize in-band DDFS induced spurs.

A fully-integrated 0.13/spl mu/m CMOS low-IF DBS satellite tuner using a ring oscillator based frequency synthesizer

The first low-IF fully-integrated tuner for DBS satellite TV applications was realized in 0.13 mum CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a coarsely defined low-IF frequency, while the second down-conversion to baseband was performed in the digital domain. Eliminating the oscillator inductors has reduced the parasitic magnetic coupling, allowing a single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant die area reduction was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL loop filter to reduce the equivalent tuning gain

A Single-chip DBS Tuner-Demodulator SoC using Discrete AGC, Continuous I/Q Correction and 200MS/s Pipeline ADCs

A digital low-IF satellite TV tuner-demodulator SoC was realized in 0.13 mum CMOS using low power 200 MS/s eight bit pipeline ADCs. A discrete-steps delayed AGC loop using FET switched-resistors resulted in a 10 dB noise figure at max gain and +25 dBm IIP3 at min gain. The image rejection correction is continuously performed in the digital domain using an inverse gain and phase mismatch adjustment. A FFT engine was used for carrier/symbol rate estimation and channel blind scanning. SoC specifications include: 0.2 dB implementation loss, <1.3degrms integrated phase noise,<-50dBc spurs, <0.2s channel acquisition time, 1.2 W power dissipation from a dual 1.8/3.3V supply and 1.8 x 4.8 mm2 die area.

A sub-1.5/spl deg/ /sub rms/ Phase-Noise Ring-Oscillator-Based Frequency Synthesizer for Low-IF Single-Chip DBS Satellite Tuner-Demodulator SoC

A fully integrated 0.13mum CMOS ring-oscillator-based PLL for low-IF single-chip DBS satellite tuner-demodulator IC is presented. A noise-attenuating loop filter reduces the oscillator gain, helping both front-end noise and spur rejection and allowing the on-chip integration of the filter capacitance. The PLL shows <1.5degrms double-sided integrated phase noise, <-60dBc reference spurs, <-50dBc coupled spurs. It occupies 0.3mm2 die area and consumes 40mA at 3.3V

A Fully-Integrated 0.13/spl mu/m CMOS Low-IF DBS Satellite Tuner

A first low-IF fully-integrated tuner for DBS satellite TV applications was realized in 0.13 mum CMOS. A wide bandwidth, ring oscillator integer-N frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a coarsely defined low-IF frequency, while the second down-conversion to base band was performed in the digital domain. Eliminating the oscillator inductors has reduced the parasitic magnetic coupling from the digital circuitry, allowing single-chip tuner-demodulator integration

Notice of Violation of IEEE Publication Principles A single-chip digitally enhanced radio receiver for DBS satellite TV applications

A digital low-IF receiver for satellite TV applications was realized in 110 nm CMOS taking advantage of high speed and moderate resolution ADCs and high digital processing power available in nanometer CMOS. A discrete gain step signal path and a digital power level measurement together with a digital AGC loop implementation resulted in lower receiver area and power and a smaller noise figure penalty. Image rejection in excess of 50 dB was achieved by using a continuous digital I/Q mismatch correction engine that relaxes the matching requirements on the analog front-end and thus reduces the occupied die area. A dynamic digital clock frequency management algorithm was implemented to avoid receiver de-sensitization due to digitally coupled in-band spurs. SoC specifications include: 0.2 dB implementation loss, <1.3degrms integrated phase noise,<-50 dBc spurs, <0.2 s channel acquisition time, 1.2 W power dissipation from a dual 1.8/3.3 V supply and 1.8 x 4.8 mm2 die area.

Notice of Violation of IEEE Publication Principles Fully-Integrated 0.13 μm CMOS Digital Low-IF DVB-S/S2 Satellite TV Tuner Using a Discrete-Step AGC Loop

A fully-integrated digital low-IF DVB-S/DVB-S2 satellite TV tuner was realized in 0.13 μm CMOS. It uses a first analog down-conversion to a sliding low-IF, followed by digitization, a second digital mixing to baseband and digital channel selection. Performing more signal processing in the digital domain lead to a relaxation of the RF front-end specifications, allowing its CMOS implementation. The digital low-IF architecture provides a digital power estimation and allows the use of a discrete-step AGC loop that results in a lower noise and linearity degradation in comparison with continuous AGC loops. Digital calibration is used throughout the DVB tuner, minimizing the gain variation over corners and relaxing the noise and linearity constraints. Partitioning the DVB-S2 receiver into a front-end tuner IC built in a mixed-signal CMOS process and a back-end demodulator and MPEG processor IC implemented in a straight digital CMOS process minimizes the receiver cost

Notice of Violation of IEEE Publication Principles A -5OdBc Spur 0.13μm CMOS Ring Oscillator PLL for DBS Satellite Receiver SOCs Using a Multi-Regulator Architecture

A fully-integrated 0.13 μm CMOS ring oscillator based PLL for digital low-IF DVB-S/S2 satellite TV tuner is presented. An attenuator loop filter reduces the oscillator gain, helping both front-end noise and spur rejection, while a noiseless resistor multiplication feed-forward architecture allows the on-chip integration of the loop filter capacitance. Eliminating oscillator inductors lead to a significant die area reduction and a low sensitivity to magnetic coupling, allowing the integration of a large digital core on the same die with the sensitive RF front-end. A multi-regulator biasing architecture was used to minimize the supply spur injection. PLL specifications include: <1.3°rms double-sided integrated phase noise from 10 KHz to 22.5 MHz, <-60 dBc reference spurs, <-50 dBc supply coupled spurs, 0.3 mm2 die area and 40 mA supply current from a 3.3 V supply

A Fully-Integrated 0.11μm CMOS Digital Low-IF DVB-S2 Satellite TV Dual Tuner SOC

A digital low-IF fully-integrated dual tuner for DVB-S2 satellite TV applications was realized in 0.11μm CMOS. It provides baseband digital I/Q outputs for a demodulator-on-host back-end processor. A wide bandwidth ring oscillator based frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a sliding low-IF frequency, while the second down-conversion to baseband was performed in the digital domain. The low-IF architecture allows a discrete AGC loop, while avoiding 1/f noise and DC offset issues. Eliminating the VCO tank inductors minimizes frequency pulling and parasitic coupling to front-end LNA, allowing the integration of a large digital core on the same die with the sensitive RF front-end.