J.M. Park

S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.

The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented. The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.

A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm DRAMs

Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si/sub 3/N/sub 4/, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) DRAMs.

High-density low-power-operating DRAM device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyond

For the first time, the DRAM device composed of 6F/sup 2/ open-bit-line memory cell with 80nm feature size is developed. Adopting 6F/sup 2/ scheme instead of customary 8F/sup 2/ scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F/sup 2/ accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F/sup 2/, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell V/sub th/ so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (sphere-shaped-recess-channel-array transistor) is introduced. It is the improved scheme of RCAT used in 8F/sup 2/ scheme. By adopting S-RCAT, V/sub th/ can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.

An outstanding and highly manufacturable 80nm DRAM technology

For the first time, fully working 512 Mb DRAMS have been developed successfully using an 80 nm DRAM technology, which is the smallest feature size in DRAM technology ever reported. With an ArF lithography, recess-channel-array-transistors (RCAT), low-temperature MIS capacitor technologies and a newly developed top spacer storage node contact (TSC), we have realized these 512 Mb DRAMS. Also, we have reduced process steps, including the layer requiring ArF lithography, by using the TSC process.

20nm DRAM: A new beginning of another revolution

For the first time, 20nm DRAM has been developed and fabricated successfully without extreme ultraviolet (EUV) lithography using the honeycomb structure (HCS) and the air-spacer technology. The cell capacitance (Cs) can be increased by 21% at the same cell size using a novel low-cost HCS technology with one argon fluoride immersion (ArF-i) lithography layer. The parasitic bit-line (BL) capacitance is reduced by 34% using an air-spacer technology whose breakdown voltage is 30% better than that of conventional technology.

Novel robust cell capacitor (Leaning Exterminated Ring type Insulator) and new storage node contact (Top Spacer Contract) for 70nm DRAM technology and beyond

For the first time, novel robust capacitor (Leaning exterminated Ring type Insulator - LERI) and new storage node (SN) contact process (Top Spacer Contact - TSC) are successfully developed with 82nm feature size. These novel processes drastically improved electrical characteristics such as cell capacitance, parasitic bit line capacitance and cell contact resistance, compared to a conventional process. The most pronounced effect using the LERI in COB structure is to greatly improve cell capacitance without twin bit failure. In addition, the TSC technology has an ability to remove a critical ArF lithography. By using the LERI and TSC processes in 82nm 512M DDR DRAM, the cell capacitance of 32fF/cell is achieved with Toxeq of 2.3nm and the parasitic bit line capacitance is reduced by 20%, resulted in great improvement of tRCD (1.5ns).

A novel robust TiN/AHO/TiN capacitor and CoSi/sub 2/ cell pad structure for 70nm stand-alone and embedded DRAM technology and beyond

For the first time, a novel robust (square-shape cylinder type) TiN/AHO (Al/sub 2/O/sub 3/-HfO/sub 2/)/TiN capacitor with Co-silicide on landing cell pad suitable for both stand-alone and embedded DRAMs are successfully developed with 88nm (pitch 176nm) feature size, which is the smallest feature size ever reported in DRAM technology, using ArF lithography for aiming 70nm stand-alone and embedded DRAM technology. The capacitor with Toxeq of 1.5nm and leakage current of less than 1 fA/cell is achieved. The cell contact resistance is greatly improved by using Co-silicidation on landing cell pad and metal storage node contact plug, which results in high performance.

A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC)

The pad-polysilicon side contact (PSC) has drastically improved the performance of the partially-insulated bulk FinFET (Pi-FinFET). PSC enabled to dope a source and drain (S/D) of the fin structure uniformly from the top of the fin to the Pi layer. Since the uniform S/D increases effective channel width, the drivability was increased by 100% compared to the conventional bulk FinFET cell. Nevertheless, hot carrier (HC) lifetime was extended because the position of the highest electric field was nearer to the gate edge compared to the conventional. The total junction leakage current became 50% of the conventional due to the Pi layer. Undoped silicon selective epitaxial growth (SEG) buffered PSC could control gate induced drain leakage (GIDL) to the same level of conventional bulk FinFET. In addition, by optimizing fin height, 25% less word line capacitance (Cwl) was achieved. We place this Pi-FinFET with PSC is one of the promising candidates for the future FinFET DRAM cell technology.

Electronic Ballast Design Driven by Low Frequency Square Wave for High Power MHL

In this paper, We proposed electronic ballast that applys Buck Converter operation principle to Full-Bridge inverter. The proposed ballast consists of an EMI Filter, a full-bridge rectifier, a passive power factor correction (PFC) circuit and a full-bridge inverter. The passive PFC is used and a Full-Bridge inverter operation by two frequency. High Side and Low Side switch was driven by high frequency and low frequency and realized buck Converter`s operation. The lamp is driven by Low Frequency square wave to avoid Acoustic Resonance. Also, bulk of inductor is reduced by high frequency switching. Performance of the proposed ballast was validated through computer simulation using Pspice, experimentation and by applying it to an electronic ballast for a prototype 700W MHL.