Young-Nam Hwang

The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond

For the first time, 512 Mb DRAMs using a Recess-Channel-Array-Transistor(RCAT) are successfully developed with 88 nm feature size, which is the smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75 nm and recessed channel depth of 150 nm exhibits drastically improved electrical characteristics such as DIBL, BV/sub DS/, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70 nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.

A 0.18 /spl mu/m 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

A non-volatile 64 Mb phase-transition RAM is developed by fully integrating a chalcogenide alloy GST (Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18 /spl mu/m CMOS technology. This alloy is programmed by resistive heating. To optimize SET/RESET distribution, a 512 kb sub-core architecture, featuring meshed ground line, is proposed. Random read access and write access for SET/RESET are 60 ns, 120 ns and 50 ns, respectively, at 3.0 and 30/spl deg/C.

S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.

Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology

Advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge2Sb2Te5 (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond

A 0.24-/spl mu/m 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme

A nonvolatile 16-kb one-transistor one-magnetic-tunnel-junction (1T1MTJ) magnetoresistance random access memory with 0.24-/spl mu/m design rules was developed by using a self-reference sensing scheme for reliable sensing margin. This self-reference sensing scheme was achieved by first storing a voltage of the magnetic tunnel junction (MTJ), and then after a time interval storing a reference voltage of the same MTJ (self-reference). The effects of variation in tunneling oxide thickness can be eliminated by this self-reference sensing scheme. As a result, reliable sensing of MRAM devices with MTJ resistance of 2.5-11 k/spl Omega/ was achieved.

The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented. The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.

A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm DRAMs

Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si/sub 3/N/sub 4/, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) DRAMs.

Programming characteristics of phase change random access memory using phase change simulations

We present a new simulation methodology for analyzing programming characteristics of a chalcogenide based phase-change device, phase change random access memory (PRAM), which is a next-generation non-volatile memory. Using the new simulation methodology, we analyze the initialization of chalcogenide material (ICM) of the mechanism and propose the next generation PRAM scheme. From the results of the phase change simulation, the process conditions for ICM for stable operation are presented. Also, the self-heating confined structure to overcome the inherent limitation of high operation power is proposed that resolves the operating power limitation associated with PRAM development.

An outstanding and highly manufacturable 80nm DRAM technology

For the first time, fully working 512 Mb DRAMS have been developed successfully using an 80 nm DRAM technology, which is the smallest feature size in DRAM technology ever reported. With an ArF lithography, recess-channel-array-transistors (RCAT), low-temperature MIS capacitor technologies and a newly developed top spacer storage node contact (TSC), we have realized these 512 Mb DRAMS. Also, we have reduced process steps, including the layer requiring ArF lithography, by using the TSC process.

20nm DRAM: A new beginning of another revolution

For the first time, 20nm DRAM has been developed and fabricated successfully without extreme ultraviolet (EUV) lithography using the honeycomb structure (HCS) and the air-spacer technology. The cell capacitance (Cs) can be increased by 21% at the same cell size using a novel low-cost HCS technology with one argon fluoride immersion (ArF-i) lithography layer. The parasitic bit-line (BL) capacitance is reduced by 34% using an air-spacer technology whose breakdown voltage is 30% better than that of conventional technology.