Byung-lyul Park

The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond

For the first time, 512 Mb DRAMs using a Recess-Channel-Array-Transistor(RCAT) are successfully developed with 88 nm feature size, which is the smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75 nm and recessed channel depth of 150 nm exhibits drastically improved electrical characteristics such as DIBL, BV/sub DS/, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70 nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.

S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.

The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented. The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.

A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm DRAMs

Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si/sub 3/N/sub 4/, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) DRAMs.

An outstanding and highly manufacturable 80nm DRAM technology

For the first time, fully working 512 Mb DRAMS have been developed successfully using an 80 nm DRAM technology, which is the smallest feature size in DRAM technology ever reported. With an ArF lithography, recess-channel-array-transistors (RCAT), low-temperature MIS capacitor technologies and a newly developed top spacer storage node contact (TSC), we have realized these 512 Mb DRAMS. Also, we have reduced process steps, including the layer requiring ArF lithography, by using the TSC process.

A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs

In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.

Annealing process and structural considerations in controlling extrusion-type defects Cu TSV

Stresses induced by the large volume of Cu in Through Silicon Vias (TSV) can result in global/local Cu extrusion which may affect reliability in 3D chip stacking technologies beyond the 28 nm node for high performance mobile devices. In this work, TSV structural factors that can influence extrusion post via filling are studied. In addition, the impact of the electroplating chemistry and annealing schemes on local extrusion type defect formation in TSVs are also studied.

Novel robust cell capacitor (Leaning Exterminated Ring type Insulator) and new storage node contact (Top Spacer Contract) for 70nm DRAM technology and beyond

For the first time, novel robust capacitor (Leaning exterminated Ring type Insulator - LERI) and new storage node (SN) contact process (Top Spacer Contact - TSC) are successfully developed with 82nm feature size. These novel processes drastically improved electrical characteristics such as cell capacitance, parasitic bit line capacitance and cell contact resistance, compared to a conventional process. The most pronounced effect using the LERI in COB structure is to greatly improve cell capacitance without twin bit failure. In addition, the TSC technology has an ability to remove a critical ArF lithography. By using the LERI and TSC processes in 82nm 512M DDR DRAM, the cell capacitance of 32fF/cell is achieved with Toxeq of 2.3nm and the parasitic bit line capacitance is reduced by 20%, resulted in great improvement of tRCD (1.5ns).

Properties of isolation liner and electrical characteristics of high aspect ratio TSV in 3D stacking technology

As semiconductor performance improvements through device scale-down becomes more difficult, 3D chip stacking technology with TSVs (Through Silicon Via) is becoming an increasingly attractive solution to achieve higher system performances by way of higher bandwidth, smaller form factor and lower power consumption. Such increase in performance using TSV aided 3D chip stacking technology applies not only to homogenous chip stacking but to heterogeneous chip stacking (e.g. memory device on logic) as well, making it ideal for such applications in high performance mobile devices.

A novel robust TiN/AHO/TiN capacitor and CoSi/sub 2/ cell pad structure for 70nm stand-alone and embedded DRAM technology and beyond

For the first time, a novel robust (square-shape cylinder type) TiN/AHO (Al/sub 2/O/sub 3/-HfO/sub 2/)/TiN capacitor with Co-silicide on landing cell pad suitable for both stand-alone and embedded DRAMs are successfully developed with 88nm (pitch 176nm) feature size, which is the smallest feature size ever reported in DRAM technology, using ArF lithography for aiming 70nm stand-alone and embedded DRAM technology. The capacitor with Toxeq of 1.5nm and leakage current of less than 1 fA/cell is achieved. The cell contact resistance is greatly improved by using Co-silicidation on landing cell pad and metal storage node contact plug, which results in high performance.