B.H. Lee

Higher permittivity rare earth doped HfO2 for sub-45-nm metal-insulator-semiconductor devices

Rare earth (RE) doping (Gd, Er, Dy) of HfO2 reduces leakage current by three orders of magnitude compared with pure HfO2. The key to reducing HfO2 leakage current and equivalent oxide thickness (EOT) is stabilization of the higher permittivity tetragonal phase. RE doping of 10–20at.% stabilizes tetragonal HfO2 and increases permittivity. The maximum permittivity achieved for HfREOx is 28. The maximum permittivity for ZrREO is 32. HfGdO metal-insulator-semiconductor capacitors with EOT=1.93nm and leakage current <1×10−8A∕cm2 after 1070°C have been demonstrated.

Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)

Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO/sub 2/ devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.

Dipole Moment Model Explaining nFET V t Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics

A dipole moment model explaining Vt tuning in HfSiON gated nFETs is proposed and its impact on performance and reliability is presented. La, Sc, Er, and Sr dopants are utilized due to their differing electronegativities and ionic radii. These dopants tune Vt in the range of 250-600 mV. Vt tuning is found to be proportional to the net dipole moment associated with the Hf-O and rare earth (RE)-O bonds at the high-k/SiO2 interface. The magnitude of this interfacial dipole moment is determined by the electronegativities and ionic radii of the RE cations. LaOx is the most effective dopant based on Vt, mobility, and reliability,

Thermally Stable N-Metal Gate MOSFETs Using La-Incorporated HfSiO Dielectric

We report a thermally stable N-metal process in which surface passivation of HfSiO dielectric using thin layers of La₂O₃, deposited by either MBE or PVD, significantly shifts the metal gate effective work function toward the Si conduction band edge. Well-behaved transistors with L_g down to 70 nm have been fabricated with threshold voltage of 0.25V, mobility up to 92% of the universal SiO₂ mobility, and T_inv ~1.6 nm

An Accurate Lifetime Analysis Methodology Incorporating Governing NBTI Mechanisms in High-k/SiO2 Gate Stacks

Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (DeltaVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric

Effective work function modification of atomic-layer-deposited-TaN film by capping layer

We demonstrate that the metallic capping layer has a strong impact on the effective work function (EWF) of the metal gate. Specifically, the EWF of atomic-layer-deposited (ALD)-TaN could be increased from 4.5to4.8eV with chemical-vapor-deposited-TiN capping, which is sufficient amount of work function modification for silicon on insulator based devices. A strong interdiffusion of Ti atoms into the ALD-TaN film is observed and correlated well with the changes in the EWF change. Ti capping experiments confirm that the Ti interdiffusion can actually modify the EWF of Ti/ALD-TaN stack.

Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow

Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN/sub x/) SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN/sub x/ for the NFET and ALD-WN/sub x/ for the PFET. Much enhanced drive current (I/sub d/) and transconductance (G/sub m/) values, and reduced off current (I/sub off/) characteristics were attained with ALD-MN/sub x/ gated devices over control poly-Si and PVD-MN/sub x/ devices within controllable V/sub t/ shifts. Excellent scalability of dual work function MN/sub x//high-k gate stack was demonstrated: the EOT was down to 6.6/spl Aring/ with low leakage in a low thermal budget device scheme.

Intrinsic Threshold Voltage Instability of the HFO2 NMOS Transistors

Electron trapping in high-k gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the pre-existing defects (fast trapping) and temperature-activated migration of trapped electrons to unoccupied traps (slow trapping). The proposed model successfully describes low temperature threshold voltage instability in NMOS transistors with HfO 2/TiN gate stacks

Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

High quality ultra-thin TM-SGOI substrate with T/sub SOI/ < 55 nm is developed to combine the device benefits of strained silicon and SOI. 80-90% Id,sat and electron mobility increase are shown in long channel nFET device. For the first time, 20-25% device performance enhancement is demonstrated at 55 nm short channel strained silicon SGOI nFET devices.

High performance gate first HfSiON dielectric satisfying 45nm node requirements

We show an ALD based HfSiON gate dielectric scaled to 1 nm EOT with excellent performance and reliability. Furthermore, the HfSiON dielectric films are integrated in a gate first approach that includes a 1000degC-5s anneal. It is also demonstrated that this 1 nm EOT HfSiON can achieve electron and hole mobilities comparable to that of SiON. This progress is enabled due to better understanding of the relationship between charge trapping, HfSiON thickness and crystallinity. Performance and reliability improvement is attributed to reduced charge trapping due to suppressed crystallization of the optimized HfSiON films