Berthold G. Bosch

Gigabit electronics—A review

Digital electronics at gigabit-per-second data rates is emerging as a new branch of science and engineering. A particular field of application opens up in advanced radar and sensing systems where large amounts of data have to be dealt with in real time. Analog-to-digital (A/D) converters with microwave sampling rates and multipliers for high-data-yield processing are specifically required subcircuits. In communications, special 1 to 2 Gbit/s systems have been developed, but a further commercial need develops in domestic satellite links and in fiber-optical communications with its potential high bandwidth capabilities. Corresponding gigabit measuring and test instrumentation is required and being implemented. Gigabit circuitry has so far mainly been realized in hybrid-integrated technology. However, the full use of modern technological tools now allows for the fabrication of gigabit monolithic integrated circuits (ICs), with circuits up to 4 Gbit/s implemented. In circuit design, specific problems must be solved which are due to the involved wide bandwidths at microwave spectral frequencies. High packing density is required for low interconnection delay, but power dissipation leads to limitations. Gigabit electronics is based on devices with switching speeds in the range of a few hundred picoseconds and lower. Besides pin diodes and Schottky diodes, transistors are investigated at first. While the Si bi-polar has been improved, it is the GaAs MESFET and the GaAs junction FET which excel in speed, with LSI capabilities. Very recently, a considerable speed improvement was reported for Si n-MOSFETs. Unique properties for gigabit logic are shown by transferred-electron devices. However, the lead with regard to high speed and low power have Josephson junctions of the in-line junction and of the interferometer types. The present phase of rapid gigabit IC development, with expected LSI circuits in the 2 to 5 Gbit/s range and MSI circuits up to 15 Gbit/s, will stimulate further applications.

Multi-Gb/s silicon bipolar clock recovery IC

A novel clock recovery IC for optical fiber communication systems with data rates up to several Gb/s is presented. It combines nonlinear signal preprocessing directly with a regenerative frequency divider scheme and an external filter in the divider loop. Hence, the center frequency of the filter and the working frequency of the amplifier are halved. The extracted clock frequency corresponds to half the bit rate, as required for many clocked circuit components within fiber optic lines. Two versions of the same IC design, scheduled for two bit rate ranges between 0.3-4 Gb/s, are realized with a conventional Si bipolar process. Clock recovery is demonstrated at 2.2 and 3.52 Gb/s, using both cavity and surface acoustic wave (SAW) filters. >

A time division multiplexer IC for bit rates up to about 2 Gbits/s

A bipolar 4:1 time-division multiplexer IC developed for a planned 1.12 Gbit/s optical communication system is presented. Without resorting to sophisticated technology, the high speed was achieved by modification of well-known circuit concepts and by careful circuit optimization. With a current-switch output, reliable operation was measured to over 2 Gbit/s compared to over 1.5 Gbit/s if emitter-follower outputs are used. The experimental results agree very well with the simulation predictions.

Silicon bipolar decision circuit handling bit rates up to 5 Gbit/s

A high-speed silicon bipolar decision circuit is presented which operates up to 5 Gbit/s. It may serve as a subcomponent for integration in a regenerator/repeater circuit for multi-gigabit fiber-optic trunk lines. The circuit was implemented in a standard bipolar silicon technology featuring oxide-wall isolation, 2-μm emitter stripe widths, and a transit frequency of 9 GHZ at V_{CE} = 1 V. The measured clock-phase-margin of the decision circuit at 4 Gbit/s corresponds to two thirds of a bit slot and to half a bit slot at 5 Gbit/s. The minimum input sensitivity at 4 Gbit/s is less than 150 mV.

A silicon bipolar 4-bit 1-Gsample/s full Nyquist A/D converter

A four-bit silicon bipolar analog-to-digital converter (ADC) which is operational at the full Nyquist input frequency up to 1 Gsample/s (Gs/s) is discussed. The effective bit number at 1 Gs/s reduces to 3.5 bits on Nyquist conditions. The 3-dB large-signal analog bandwidth is 800 MHz and the maximum sampling rate reaches 2 Gs/s and beyond. The converter is built up by stacking of two three-bit subcircuits. The ADC architecture relies on a balanced structure mixing conventional flash-converter elements with analog encoding. Total power consumption is 2.4 W. Standard silicon bipolar technology is used without self-alignment. >

Diode Circuits for Pulse Regeneration and Multiplexing at Ultrahigh Bit Rates

Clocked step-recovery diode (SRD) circuits are investigated for regenerating and multiplexing PCM-type signals in the range from 0.1 to a few gigabits per second. One regenerator type is particularly suited for operating with signals in the 1-V range, whereas a differential version employing a magic T was developed for handling signals of down to about 5 mV. By making use of line transformers as coupling networks, high-level versions have been cascaded. Experiments performed at 0.3 and 1 Gbit/s yielded voltage amplifications (peak amplitudes) of 2.5-5.5 for single stages, and insertion power gains of 7-11 dB for 2-3 stage cascades. Diode stages have also been used for multiplexing 4 and 2 individual bit streams to give a combined output signal at 1 and 2 Gbit/s, respectively. In a preliminary multiplexer experiment an output at 4.5 Gbit/s was obtained. Finally, possibilities are discussed for improving the performance of the regenerators/multiplexers and for their applications.

Base contact resistance limits to lateral scaling of fully self-aligned double mesa SiGe-HBTs

Abstract A significant reduction of parasitic resistances and capacitances of the double mesa SiGe Heterojunction Bipolar Transistors (SiGe-HBT) was achieved by using self-aligned processing steps, such as planarization of transistor contacts, outside-spacer-technology for micromasking, contact implantation and low ohmic silicidation. This article presents and analyses the lateral optimization of the double mesa SiGe-HBT by on-wafer measurements and demonstrates lateral scaling limitation resulting from the increasing base metal-semiconductor contact resistance. The increase of the more important base contact resistance is proven by two-dimensional contact simulation. This is shown experimentally by using a fully self-aligned double mesa SiGe-HBT transistor which combines the advantages of superior high frequency characteristics with a simple and low cost fabrication procedure being used mainly in compound semiconductor technology.

Injection Laser Modulation At 2 Gbit/s by Monolithic Silicon Multiplexer

Direct laser-diode pulse-code modulation at 2 Gbit/s (NRZ) is performed by a fast Si monolithic integrated bipolar circuit (2.5-µm design rules, p-n-junction isolation, f/sub 1/ /spl ap/ 7 GHz at V/sub CE/=1 V). The current-switch output stage of a 4:1-time-division multiplexer IC feeds a modulation current swing of 8 mA into a CSP injection laser biased above threshold. Measured optical responses of the laser are reported.

Silicon Clock Recovery IC's for 2 to 3.5 Gbit/s

A novel clock recovery IC for Gbit/s optical communication is presented, employing a 1:2 dynamic frequency divider scheme with an external resonator filter. It is based on a conventional Si bipolar process. Two versions of the same IC design are presented, one optimized for 2 to 3 Gbit/s, the other for 3 to 4 Gbit/s. Clock recovery is demonstrated at 2.23 and 3.52 Gbit/s, leading to clock signals of 1.115 and 1.76 GHz, respectively. Measured rms clock phase jitter is less than 0.3°.

Gigabit Electronics - Present State and Trends

Application fields for Gb/s electronics, with high-throughput signal processing as the prime motive, are indicated. Recent implementations of Gb/s ICs are mentioned. After describing and commenting on the multitude of silicon and GaAs approaches, a projection on their ultimate functional throughput rate (FTR) is attempted, based on present experimental data. In a similar way, the possibilities of Josephson technology are analyzed.