J.P. McVittie

Thin-oxide damage from gate charging during plasma processing

The plasma-induced charge damage to small gate gate MOS capacitors is investigated by using antenna structures. After an O/sub 2/ plasma step the interface state density increases with increasing antenna area and varies by two orders of magnitude. A hole trapping-induced breakdown mechanism during plasma charging is supported by experimental evidence which includes annealing and polarity effects for charge to breakdown and tunneling currents. In addition, oxide susceptibility is shown to depend on oxide growth conditions and is predictable by negative bias-temperature aging.<<ETX>>

Air-gap formation during IMD deposition to lower interconnect capacitance

The use of air-gaps between interconnect metal lines to reduce interconnect capacitance has been explored. Simulations were performed to determine the reduction in capacitance obtainable using air-gaps. The formation of air-gaps in the isolation oxide between metal lines was simulated using Stanford Profile Emulator for Etching and Deposition in IC Engineering (SPEEDIE). The capacitance of the SPEEDIE profiles was then extracted using Raphael (an electrical analysis simulator from TMA). The feasibility of air-gaps was also demonstrated experimentally. Fabricated air-gap structures exhibited a 40% reduction in capacitance when compared to a HDP-CVD oxide gap-fill process with K=4.1. Additionally, the air-gap structures did not exhibit any appreciable leakage current.

A model and experiments for thin oxide damage from wafer charging in magnetron plasmas

A physically based model that has been developed to explain the role of plasma nonuniformity in charge damage to oxides is presented. For a uniform plasma the local conduction currents to the water surface integrate to zero over the RF period, and the surface charging is sufficient to damage oxides. For the case of thin oxides under a gate exposed to a nonuniform magnetron plasma, the gate surface can charge up until the oxide tunneling current balances the difference in the mean local conduction currents from the plasma. It is this oxide current that leads to degradation. The oxide current obtained via SPICE circuit simulations, probe measurements and breakdown measurements shows good agreement with experimental damage data of antenna capacitors.<<ETX>>

A 3‐dimensional model for low‐pressure chemical‐vapor‐deposition step coverage in trenches and circular vias

A general analytical model has been developed to calculate particle transport and spatial step coverage evolution within 2‐dimensional and 3‐dimensional microelectronic device structures during low‐pressure chemical vapor deposition. The model can account for spatially dependent nonunity reactive ‘‘sticking probabilities,’’ anisotropic source fluxes, and trench ‘‘shadowing’’ effects. There is no restriction on the initial and evolving shape of the structure. Model results are compared to direct Monte Carlo simulations for step coverage on rectangular trenches, and are found to more accurately describe the observed experimental step coverages during phosphorous‐doped silicon dioxide glass film deposition. We present here, for the first time, detailed calculations of step coverage in circular vias for a wide range of reactive sticking probabilities.

Radical oxidation of germanium for interface gate dielectric GeO2 formation in metal-insulator-semiconductor gate stack

GeO2 was grown by a slot-plane-antenna (SPA) high density radical oxidation, and the oxidation kinetics of radical oxidation GeO2 was examined. By the SPA radical oxidation, no substrate orientation dependence of growth rate attributed to highly reactive oxygen radicals with low oxidation activation energy was demonstrated, which is highly beneficial to three-dimensional structure devices, such as multigate field-effect transistors, to form conformal gate dielectrics. The electrical properties of an aluminum oxide (Al2O3) metal-oxide-semiconductor gate stack with a GeO2 interfacial layer were investigated, showing very low interface state density (Dit), 1.4×1011u2002cm−2u2009eV−1. By synchrotron radiation photoemission spectroscopy, the conduction and the valence band offsets of GeO2 with respect to Ge were estimated to be 1.2±0.3 and 3.6±0.1u2002eV, which are sufficiently high to suppress gate leakage.

An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory

We demonstrate a novel phase change memory cell utilizing doped Ge nanowire pn-junction diode both as a bottom electrode and a memory cell selection device. This memory cell can be used for a cross-point memory array with diode selection. Using selective growth of isolated vertical nanowires in each cell, we have minimized the contact area below the lithography limit. A very low SET programming current of 10s of muA was achieved. RESET/SET resistance ratio of 100x was obtained. The diode provides 100x isolation between forward and reverse bias in the SET state.

Resistive Switching Mechanism in

Nonvolatile information storage devices based on an abrupt resistance switch when an electric bias is applied are very attractive for future memory applications. Recently, such a resistance switch was described in ferroelectric ZnxCd1-xS, but the mechanism of switching remains controversial. Here, we present results that elucidate the mechanism, showing that a metal needs to be easily oxidized and is capable of diffusing into the ZnCdS film as a cation impurity forming a filamentary metallic conduction path

\hbox{Zn}_{x}\hbox{Cd}_{1 - x}\hbox{S}

The highest electron mobility to-date in Ge is reported. For the first time, the effect of surface orientation on mobility is investigated experimentally. Carrier scattering mechanisms are studied through low temperature mobility measurements. Ozone-oxidation has been introduced to engineer Ge/insulator interface. Minimum density of interface states (DD_it) of 3x10¹¹ cm^-2 V^-1 is demonstrated and D_it across the bandgap is extracted.

Nonvolatile Memory Devices

The low‐pressure deposition of SiO2 from tetraethylorthosilicate (TEOS) is studied. Experiments have been done to get the profile evolution in trenches of different aspect ratios and at various time steps until closure. A fast analytical simulator, using an adsorption/reemission model, which can handle multiple species, has been developed to simulate the profile evolution. The deposition profiles were simulated using a single or a two rate limiting precursor model. It has been previously shown that low‐pressure chemical vapor deposition (LPCVD) of SiO2 from other sources, such as silane, can be modeled accurately using only one rate limiting precursor. Comparison of simulation results and experimental profiles of LPCVD of SiO2 from TEOS indicates that a deposition model which includes two rate limiting precursors is consistent with experiments. It is suggested that an intermediate species, having a very high reaction sticking coefficient (Sc∼1), is likely to be formed by gas phase reactions. This along wi...

Interface-Engineered Ge (100) and (111), N- and P-FETs with High Mobility

For the first time, high performance Ge nMOSFET is fabricated using laser annealing of ion-implanted antimony (Sb) dopants which provides donor activation beyond 1×10²⁰cm⁻³ in germanium. Record I<inf>on</inf>/I<inf>off</inf> > 10⁵ is demonstrated for n⁺/p junctions combined with significant reduction of contact resistance to 7×10⁻⁷ Ω-cm². Performance projections for ITRS HP 22nm technology node are also discussed.