J.R. Heath

Discrete event system approach for delay fault analysis in digital circuits

This paper presents the application of discrete event system (DES) techniques to delay fault modeling and analysis. DES is a dynamical system that evolves according to asynchronous occurrence of certain discrete changes, called events. An integrated circuit (chip) may be considered as a discrete event system. DES modeling techniques are used for delay fault analysis of a chip design. This formal analysis technique may help avoid some of the large cost of simulation, DES delay gate models and circuit path delay models are developed as well as algorithms that provide design testability evaluation and robust delay fault test generation.

Influence of weed maturity levels on species classification using machine vision

Abstract The environmental effect of weed control systems has stimulated research into new practices for weed control, such as selective herbicide application methods on weed-infested crop areas. This research used the color co-occurrence method (CCM) texture analysis to determine the effects of plant maturity on the accuracy of weed species classification of digitized images. Two different experimental combinations of weed species and maturity level were examined. The weed species evaluated were ivyleaf morningglory, giant foxtail, large crabgrass, and velvetleaf, with soil image sets added to each experiment. One study examined classification accuracies for two weed species at three maturity levels, and the second study examined four weed species at two maturity levels. For each species-maturity level combination, 40 digital images were collected from a manually seeded outdoor plant bed. Digitized images were transformed from the red–green–blue (RGB) color format into hue–saturation–intensity (HSI) format to generate CCM texture feature data. Stepwise variable reduction procedures were used to select texture variables with the greatest discriminant capacity. Then discriminant analysis was used to determine the classification accuracy for the two different experiments. When using HSI texture statistics, discriminant analysis correctly classified weed species within and across maturity levels with an accuracy above 97% for both experimental groups. These image processing algorithms demonstrate potential use for weed scouting, weed infestation mapping, and weed control applications using site-specific farming technology. Nomenclature: Ivyleaf morningglory, Ipomoea hederacea (L.) Jacq. IPOHE; giant foxtail, Setaria faberi Hermm. SETFA; large crabgrass, Digitaria sanguinalis (L.) Scop. DIGSA; velvetleaf, Abutilon theophrasti Medik. ABUTH.

Methodology for synthesis, testing, and verification of pipelined architecture processors from behavioral-level-only HDL code and a case study example

A goal of computer designers is to reduce the development cycle time for complex pipelined architecture core processor systems. A research effort is described which had a major objective of determining if an approach and methodology could be developed which will allow complex pipelined architecture processors with stringent system functional, timing, and performance requirements to be correctly and efficiently synthesized from a high behavioral-level-only HDL design description, thus reducing development cycle time. A second research objective was to synthesize to target FPGA technology using primarily standard available PC based CAD tools. Contributions include a developed approach and methodology which are verified by presentation of the results of a case study example which resulted in the correct synthesis of a FPGA prototype of a behavioral-level-only HDL described pipeline architecture processor. Correct synthesis was verified via experimental testing of the processor prototype.

Realization of digital filters using input-scaled floating-point arithmetic

Fixed-point and floating-point realizations of digital filters are abundant in the literature of digital signal processing. A block-floating-point realization which has some advantages of both fixed-point and floating-point has been reported and compared to fixed-point and floating-point arithmetic with regard to roundoff noise effects. In this paper another alternative realization is proposed which uses input-scaled floating-point arithmetic. A mathematical model is first developed which has some characteristics of both fixed-point and floating-point realizations. Design considerations and theoretical analysis techniques which apply to an input-scaled floating-point realization are presented. A noise model comparison of input-scaled floating-point and block-floating-point realizations is made. Finally, an input-scaled floating-point realization is implemented with a minicomputer and experimental results are shown. It is concluded from the experimental implementation that an input-scaled floating-point structure is a feasible concept which can be implemented with the simplicity of a fixed-point realization, yet it exhibits some desirable characteristics of both fixed-point and floating-point realizations. Also, the implementation of an input-scaled floating-point realization should be simpler than that of block-floating-point because of the simpler scale factor of the former, and an input-scaled floating-point realization characteristically has fewer noise sources than a block-floating-point realization.

PARALLEX: a parallel approach to switchbox routing

A parallel algorithm, called PARALLEX, which uses a conflict resolving method, has been developed for the switchbox routing problem in a parallel processing environment. PARALLEX can achieve a very high degree of parallelism by generating as many processes as nets. Each process is assigned to route a net, which bears the same identification number as the process. If conflicts are found for the current route of a net, then that process classifies the set(s) of conflict segments into groups that are identified by the various types of conflict(s) within each group. Each process with conflicts finds partial solutions by resolving every conflict of a group in the path-finding procedure and merges them with the solutions from other processes, which may or may not have conflicts, to make a conflict-free switchbox. The speed-up for 7and 19-net problems were 4.7 and 10, respectively. >

A Hand-Held Programmable-Logic-Device Based Temperature and Relative-Humidity Sensor, Processor and Display System Platform for Automation and Control of Industry Processes

The development, testing, and validation of a small versatile battery-powered handheld programmable-logic-device (PLD)-based temperature and relative-humidity (RH) sensor, processor, and display system platform is addressed in this paper. An initial and illustrative application of the platform, which is used for its validation-temperature and RH sensing, calculation, and display of equilibrium moisture content of wood, is described. The platform may be utilized for computation and display of a range of temperature- and RH-sensitive metrics/parameters of importance to other process industries. The cost of the platform is important but not the highest priority. As illustrated in the wood-process-industry application of the platform, a higher priority is an ability to efficiently explore, implement, and compare, in a timely manner, different processor microarchitectures and display system formats which may be used in the calculation and display of any process-industry temperature- and/or RH-dependent process metric(s). This could include simultaneous calculation and display of multiple metrics which are a function of temperature and RH. After comparison, a best processor microarchitecture and display system can then be chosen and implemented based on specific industry process application performance/cost and other requirements. A PLD-based sensor, processor, and display system platform offers this opportunity.

Modeling, design, virtual and physical prototyping, testing, and verification of a multifunctional processor queue for a single-chip multiprocessor architecture

Critical to run-time processor resource allocation, reconfiguration, and control of a reconfigurable heterogeneous single-chip multiprocessor architecture is a defined multifunctional queue required by each processor of the architecture. The multifunctional queue implements six functions required for control, resource allocation, and reconfiguration within the architecture. In addition to normal queue functionality of First In First Out (FIFO) operation and empty/full indicator, the multifunctional queue implements the additional non-common functions of indicating when queue depth has reached a programmable threshold level, it indicates queue occupancy level at all times, it continually indicates queue input rate over a programmable time interval, it continually indicates queue input rate change over a programmable time interval and it can implement a pseudo-RAM function. An analytic functional model of the queue is first presented then an organization, architecture and design is developed followed by the development of appropriate analytic real-time performance metrics for the queue. Both virtual and Field Programmable Gate array (FPGA) based prototypes of the queue are then developed and used for functional, maximum frequency, and/or performance model testing resulting in verification of desired queue functionality and performance. A contribution of the queue is its functional versatility which would allow its use in computer architectures or processors other than the described target architecture.

Implementation and verification of the feedback control software function of a switched reluctance cycloconverter controller

This paper addresses the implementation of the control algorithm for a 400 Hz AC switched reluctance cycloconverter (SRC). The paper develops the general framework for the implementation of the complete controller which consists of two main components: a digital signal processor (DSP) and a complex programmable logic device (CPLD). This paper focuses on the DSP part of the controller and in particular the software. The part of the control algorithm implemented with the DSP were programmed in C. The paper describes how a Simulink test environment was used to verify the DSP portion of the controller and in particular was used to verify that the C software running on the DSP can successfully control the 400 Hz AC SRC.

Delay fault testability modeling with temporal logic

To ensure the quality of manufactured integrated circuits, it is important that designs be delay fault testable. A formal verification technique such as temporal logic can help avoid the large cost of dynamic simulation. Temporal logic is a formalism for evaluating the temporal behavior of systems. STeP, Stanford Temporal Prover, is a system developed at Stanford University to support computer-aided formal verification of concurrent and reactive systems based on temporal logic specification. The application of temporal logic and STeP to delay fault testability modeling and analysis is presented.

A methodology for the control and custom VLSI implementation of large-scale Clos networks

A control algorithm is developed and implemented for a three-stage Clos network which results in using a multiple-chip approach. The system will be nonblocking in the strict sense and completely self-routing, i.e. the controller for the network will reside in the network and not in a separate computer that runs a program that controls switches to the interconnect array. Intermodule communication required for network operation is described followed by a discussion of how the number of network inputs/outputs may be varied. A delay model of the network is developed.<<ETX>>