M. Fallon

Numerical analysis of the effect of geometry on the performance of the Greek cross structure

This paper examines the effect that geometry has upon the value of resistivity that is extracted from Greek cross type structures. This work suggests that structure to structure variability of the Greek cross can be reduced through the choice of the appropriate layout.

Examination of LOCOS process parameters and the measurement of effective width

Device isolation by means of LOCOS and field implantation are commonly incorporated in current MOS processes. These two process steps interact to affect the effective MOS transistor width. The authors examine the topographical features determined by pad oxide and nitride thicknesses and compare the physical with the effective electrical width. It is concluded that the limit in topographical packing density may be achieved by physical reduction of the birds beak, but for varying pad oxide/nitride mask combinations the effective device width is limited by the presence of the field implant.<<ETX>>

An interconnect scheme for reducing the number of contact pads on process control chips

An approach is presented to reduce the number of pads required by electrical test structures by using a multiplexed interconnect scheme. This passive multiplexed scheme requires only two levels of interconnect and can be used for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks. The basic measurement procedure to access individual components is to force a voltage on one of the access pads and then ground one of the group terminals via an ammeter. While an even number of pads is not mandatory it is recommended since this maximizes the efficiency of pad usage. >

Test structures for characterising a damascene CMP interconnect process

This paper presents some test structures that can be used to help characterize interconnect fabricated using a CMP damascene process. Electrical measurements of the test structures are compared with those obtained using an AFM and surface profiling.

A test structure for the measurement of planarisation

This paper presents simulations of a test structure that can be used to assess the degree of planarisation of inter-layer dielectrics. It consists of sets of comb structures separated by a dielectric. For each structure the combs on the two layers overlap each other with adjacent structures having the overlap in one direction progressionally offset by 0.2 /spl mu/m. The capacitance of these structures is then measured from which the degree of planarisation can be assessed. This structure has potential applications for characterising Chemical Mechanical Polishing (CMP) processes for multi-level VLSI applications.

Integration of costing, yield and performance metrics into the TCAD environment through the combination of DOE and RSM

This paper details a procedure that uses a Total TCAD framework for producing costing and yield response surfaces in addition to the normal performance related information. It uses CALPHURNIA to integrate the simulation and experimental design software into the same environment. In addition to the transfer of data between the two packages, CALPHURNIA also automates the fitting of response surfaces and the creation of response distribution information for the design of robust processes. CAESAR is used to manage the process, device and circuit simulators while RS/1 performs the experimental design role. The costing and yield information is held as formulas within RS/1 which, when combined with the process details, can produce response surfaces of cost information that can be used to help the process designer select the most appropriate operating region.

Wafer mapping using DOE and RSM techniques

This paper applies classical DOE techniques to the the selection of measurement points for wafer mapping. RSM is used to generate the contour plots and it is shown that in many cases transformations can be used to improve the accuracy of wafer maps.

Analysis of current flow in mono-crystalline electrical linewidth structures

The current flow in lightly doped mono-crystalline silicon structures designed for use as low cost secondary reference linewidth standards is investigated. It is demonstrated that surface charge can have a significant effect upon the measurements of linewidth test structures. The effect of surface charge on <110> Greek cross structures is also investigated and the influence of a gate electrode on the extracted value of sheet resistance demonstrated. It is confirmed that the resulting uncertainty in both of these measurements can be simply overcome by degenerately doping the silicon during the fabrication process.

An electrical test structure for the measurement of planarization

This paper presents the simulation and experimental measurements of an electrical test structure that can be used to assess the degree of planarization of interlayer dielectrics. It consists of two sets of metal combs separated by a dielectric. For each structure the combs on the two layers overlap each other, with adjacent structures having the overlap in one direction progressionally offset by 0.2 /spl mu/m. The capacitance of these structures is then measured, from which the degree of planarization can be assessed. This structure has potential applications for characterising chemical mechanical polishing (CMP) processes for multilevel very large scale integration (VLSI) applications.

Electrical assessment of planarisation for CMP [inter-layer dielectrics]

Experimental measurements of an electrical test structure for use in assessment of the degree of planarisation of inter-layer dielectrics are presented and compared with theoretical predictions. The test structure consists of two sets of metal combs separated by a dielectric. For each structure the combs on the two layers overlap each other by some degree, with adjacent structures having the overlap in one direction progressionally offset by 0.2 /spl mu/m. It is demonstrated theoretically that the structure is robust to expected levels of oxide thickness variation.