Ja-hum Ku

Study of ZrO2 thin films for gate oxide applications

We investigated the microstructures and electrical properties of ZrO2 films deposited by reactive dc magnetron sputtering on Si substrates for gate dielectrics applications. We observed that the refractive index value of the ZrO2 films increased with an increase in deposition powers and annealing temperatures. The ZrO2 films deposited at elevated temperatures are polycrystalline, and both the monoclinic and tetragonal phases exist in the films. Films with higher density and improved crystallinity are obtained at higher deposition temperatures. The interfacial oxide layer between ZrO2 films and Si substrates grew upon annealing in the O2 gas ambient, which is due to the oxidation of Si substrates by the diffusion of oxidizing species from O2 gas ambient. The accumulation capacitance value increased upon annealing in the N2 gas ambient due to the densification of the films, while it decreased in O2 gas ambient due to the growth of the interfacial oxide layer.

Impact of mechanical stress engineering on flicker noise characteristics

Relationship between mechanical stress engineering and flicker noise are clarified for the first time using a 50nm level CMOS technology. It is found that enhanced mechanical stress degrades flicker noise characteristics. Trap states and dipoles generated by the stress are considered to be the cause of degradation. The transistor performance enhancement with flicker noise reduction by nitrogen profile optimization in gate dielectric is demonstrated as a countermeasure.

A study on the microstructure and electrical properties of CeO2 thin films for gate dielectric applications

Abstract We investigated the evolution of microstructures and the #electrical properties of CeO 2 thin films deposited by the reactive DC magnetron sputtering method on the (100) silicon substrate upon annealing in the O 2 gas ambient. The CeO 2 thin films deposited at 300°C were polycrystalline. After annealing in ambient O 2 gas, the crystallinity of the CeO 2 film was improved and becomes more dense with annealing time and temperature. The maximum accumulation capacitance of CeO 2 thin film annealed above 700°C in the ambient O 2 gas decreased due to the growth of the interfacial SiO 2 layer between CeO 2 film and silicon substrate by the diffusion of oxidizing species through CeO 2 thin film from the ambient gas.

High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

An aggressively scaled high performance 45 nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through innovative utilization and integration of advanced stressors, thermal processes and other technology elements, at aggressively scaled 45 nm design ground rules, core NFET and PFET realized world leading drive currents of 1150 and 785 uA/um at 100 nA/um off current at IV, respectively. In addition to the high performance transistors, an ultra low-k back-end dielectric (k=2.4) significantly lowers wiring delay. In this technology, CMOS transistors with multiple-oxide thicknesses are supported for low leakage and I/O operations, and competitive SRAM is offered.

17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization

The power consumption of a mobile application processor (AP) is strongly limited by the SRAM minimum operating voltage, VMIN [1], since the 6T bit cell must balance between write-ability and bit cell stability. However, the SRAM VMIN scales down gradually with advanced process nodes due to increased variability. This is evident with the quantized device-width and limited process-knobs of a FinFET technology, which has greatly affected SRAM design [2-4]. Therefore, assist-circuits are more crucial in a FinFET technology to improve VMIN, which in turn adds to the Power, Performance, and Area (PPA) gain of SRAM.

Thermal stability of Al- and Zr-doped HfO2 thin films grown by direct current magnetron sputtering

Ultrathin HfO2 dielectric films doped with Al and Zr were grown on p-type Si(100) substrates by dc magnetron sputtering, and their microstructural and electrical properties were examined. Compositions and chemical states of the dielectric films were analyzed by Rutherford backscattering spectrometry and x-ray photoelectron spectroscopy. The HfO2 films doped with Zr were crystallized even from the as-deposited state, however, the crystallization temperature of the HfO2 film doped with 16% Al2O3 was delayed up to 900 °C. As the annealing temperature increases, high-resolution transmission electron microscopy analyses of all doped HfO2 films showed an increase of the interfacial layer thickness due to the diffusion of small partial pressure of oxygen in annealing ambient. Our results also showed that the addition of Al2O3 to 14% is not useful for blocking the oxygen diffusion through the (HfO2)0.86(Al2O3)0.14 film. From the capacitance-voltage measurements, the dielectric constants of the Al- and Zr-doped Hf...

A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology

Device performance has been boosted by integrating dual-stress-liners (DSL) in a 45nm low power platform as a cost effective approach. A stress-proximity-technique (SPT) has been explored to improve device performance without adding process complexity. Record drain currents of 840/490 muA/mum have been achieved for NMOS and PMOS, respectively, at 1.2V and off-leakage current of 1nA/mum. Junction profiles have been optimized to reduce the gate-induced-drain-leakage (GIDL). An asymmetric IO has been integrated into this low power technology for the first time, offering multiple advantages including low cost, performance gain up to 30% and reliability improvement as well

Mass-productive ultra-low temperature ALD SiO/sub 2/ process promising for sub-90 nm memory and logic devices

For the first time, ultra-low temperature ALD SiO/sub 2/ is successfully developed and applied on W/WN/poly-Si stack gates as a dual spacer for the enhancement of data retention time. ALD SiO/sub 2/ deposition is performed at 75/spl deg/C using HCD and H/sub 2/O as precursors and pyridine as a catalyst. Using the ALD SiO/sub 2/ process, SiO/sub 2/ layers are deposited on W/WN/poly-Si stack gates without W oxidation. The gate resistances of the W/WN/poly-Si stack gates do not exhibit any difference between SiN single spacer and SiO/sub 2//SiN dual spacer schemes, which indicates that W oxidation does not occur during the ALD SiO/sub 2/ deposition for dual spacer formation. Conclusively, the significant improvement (>50%) of data retention time is achieved by employing SiO/sub 2//SiN dual spacers at W/WN/poly-Si stack gates in a 130 nm DRAM device. In addition, excellent short channel characteristics of Vth are identified by applying a low temperature ALD SiO/sub 2/ layer as a dual spacer on sub-100 nm SRAM devices.

Model based OPC for implant layer patterning considering wafer topography proximity (W3D) effects

Implant layer patterning is becoming challenging with node shrink due to decreasing critical dimension (CD) and usage of non-uniform reflective substrates without bottom anti-reflection coating (BARC). Conventional OPC models are calibrated on a uniform silicon substrate and the model does not consider any wafer topography proximity effects from sub-layers. So the existing planar OPC model cannot predict the sub-layer effects such as reflection and scattering of light from substrate and non-uniform interfaces. This is insufficient for layers without BARC, e.g., implant layer, as technology node shrinks. For 45-nm and larger nodes, the wafer topography proximity effects in implant layer have been ignored or compensated using rule based OPC. When the node reached 40 nm and below, the sub-layer effects cause undesired CD variation and resist profile change. Hence, it is necessary to model the wafer topography proximity effects accurately and compensate them by model based OPC. Rigorous models can calculate the wafer topography proximity effects quite accurately if well calibrated. However, the run time for model calibration and OPC compensation are long by rigorous models and they are not suitable for full chip applications. In this paper, we demonstrate an accurate and rapid method that considers wafer topography proximity effects using a kernel based model. We also demonstrate application of this model for full chip OPC on implant layers.

Ultimate solution for low thermal budget gate spacer and etch stopper to retard short channel effect in sub-90 nm devices

For the first time, by employing low thermal budget processes of ALD SiO/sub 2/ and ALD SiN as gate spacer and silicide blocking layer, the short channel effects of CMOSFETs are significantly suppressed. Using the ALD SiO/sub 2/ and ALD SiN processes, we achieved excellent roll-off characteristics of threshold voltage in PMOS, which results in 10% increase of drive current and 15% decrease of inverter delay time. Furthermore, gate oxide reliability and static noise margin of 6T-SRAM bit cell with ALD SiC/sub 2/SiN processes are comparable to those with conventional high temperature CVD SiO/sub 2//SiN processes. In conclusion, ALD SiO/sub 2/ and ALD SiN processes of extremely low thermal budget are successfully implemented to sub-90 nm CMOSFETs.