Min-Chul Sun

Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field- effect transistor (I-HTFET) adopting Ge-AlxGa1-xAs- Ge system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2). Index Terms—Tunneling field-effect transistor (TFET), Type-I heterojunction, narrow bandgap material, high mobility, simulation, nanowire, high performance (HP) logic technology

Schottky Barrier Tunnel Field-Effect Transistor using Spacer Technique

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and shortchannel SBTFET .

Charge injection from gate electrode by simultaneous stress of optical and electrical biases in HfInZnO amorphous oxide thin film transistor

A comprehensive study is done regarding stabilities under simultaneous stress of light and dc-bias in amorphous hafnium-indium-zinc-oxide thin film transistors. The positive threshold voltage (Vth) shift is observed after negative gate bias and light stress, and it is completely different from widely accepted phenomenon which explains that negative-bias stress results in Vth shift in the left direction by bias-induced hole-trapping. Gate current measurement is performed to explain the unusual positive Vth shift under simultaneous application of light and negative gate bias. As a result, it is clearly found that the positive Vth shift is derived from electron injection from gate electrode to gate insulator.

Simulation Study on Silicon-Based Floating Body Synaptic Transistor with Short- and Long-Term Memory Functions and Its Spike Timing-Dependent Plasticity

In this work, a novel silicon (Si) based floating body synaptic transistor (SFST) is studied to mimic the transition from short-term memory to long-term one in the biological system. The structure of the proposed SFST is based on an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with floating body and charge storage layer which provide the functions of short- and long-term memories, respectively. It has very similar characteristics with those of the biological memory system in the sense that the transition between short- and long-term memories is performed by the repetitive learning. Spike timing-dependent plasticity (STDP) characteristics are closely investigated for the SFST device. It has been found from the simulation results that the connectivity between pre- and post-synaptic neurons has strong dependence on the relative spike timing among electrical signals. In addition, the neuromorphic system having direct connection between the SFST devices and neuron circuits are designed.

GaN-based light emitting diodes using p-type trench structure for improving internal quantum efficiency

In order to improve the internal quantum efficiency of GaN-based LEDs, a LED structure featuring a p-type trench in the multi-quantum well (MQW) is proposed. This structure has effects on spreading holes into the MQW and reducing the quantum-confined stark effect (QCSE). In addition, two simple fabrication methods using electron-beam (e-beam) lithography or selective wet etching for manufacturing the p-type structure are also proposed. From the measurement results of the manufactured GaN-based LEDs, it is confirmed that the proposed structure using e-beam lithography or selective wet etching shows improved light output power compared to the conventional structure because of more uniform hole distribution. It is also confirmed that the proposed structure formed by e-beam lithography has a significant effect on strain relaxation and reduction in the QCSE from the electro-luminescence measurement.

Scalable embedded Ge-junction vertical-channel tunneling field-effect transistor for low-voltage operation

While a tunneling field-effect transistor (TFET) is an attractive candidate for sub-20 nm ultra-low-power device, high ION/IOFF and on-current are rarely reported with the deep-submicron structures. In this study, we propose a practical novel TFET structure with vertical channel and Ge junction, which shows high current ratio, low subthreshold swing and relatively high current even when the minimum device dimension is smaller than 20 nm. To find the optimum design, the off-state injection of a short-channel TFET and optimization of the source-side junction are studied by simulation.

Process Considerations for 80-GHz High-Performance p-i-n Silicon Photodetector for Optical Interconnect

In this work, design considerations for highperformance silicon photodetector are thoroughly investi- gated. Besides the critical dimensions of device, guidelines for process architecture are suggested. Abiding by those criteria for improving both direct-current (DC) and alternating-current (AC) perfor- mances, a high-speed low-operation power silicon photodetector based on p-i-n structure for optical interconnect has been designed by device simulation. An f-3dB of 80 ㎓ at an operating voltage of 1 V was obtained.

A tunneling field-effect transistor using side metal gate/high-k material for low power application

Supply voltage (VDD) scaling has been an important issue as the CMOS scaling down. Scaling of devices induces large leakage current due to Short Channel Effects (SCEs). Also, Subthrehold Swing (SS) value of CMOS devices is theoretically limited to 60 mV/dec. Various structures have been proposed to overcome power dissipation problems, one of which is the TFETs [1–2]. However, TFET has two critical drawbacks such as low on-current level and ambipolar behaviors. To overcome these disadvantages, TFET using hetero-gate dielectric materials has been lately reported [3]. Although this TFET has low SS and high on-current level, it is difficult to control dielectric alignment between high-k material and SiO2 in the process. Thus, we introduce an improved TFET in terms of fabrication and performance.

Silicon Tunneling Field Effect Transistors with a Hemicylindrical Nanowire Channel for Ultra-Low Power Application

In order to decrease the threshold voltage while maintaining the OFF current low, reduction of the subthreshold swing is essential in field effect transistors(FETs). To reduce the subthreshold swing below 60 mV/decade, inter-band tunneling can be used for injection of carriers and the device that utilizes such a mechanism is tunneling field effect transistor (TFET). Silicon(Si) TFETs, which are favored due to their compatibility with currently dominant complementary metal-oxide-semiconductor(CMOS) technology, suffer from low ON current because of the relatively large bandgap of Si. The ON current of Si TFETs can be increased by field and area enhancement in a cylindrical nanowire channel. Numerical analysis has confirmed that the cylindrical channel structure shows significantly higher tunneling rate and wider tunneling area than the double gate structure. Si TFETs with a hemicylindrical nanowire channel are fabricated and characterized, and the effectiveness of nanowire channel approach is demonstrated.

V T -Modulation of Planar Tunnel Field-Effect Transistors with Ground-Plane under Ultrathin Body and Bottom Oxide

Control of threshold voltage (V T ) by ground-plane (GP) technique for planar tunnel fieldeffect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For V T -modulation larger than 100 mV, heavy ground doping over 1×1020 cm -3 or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common V T -control scheme when these devices are co-integrated.