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Dive into the research topics where Kwan-Jong Roh is active.

Publication


Featured researches published by Kwan-Jong Roh.


symposium on vlsi technology | 2003

Thermally robust Ta-doped Ni SALICIDE process promising for sub-50 nm CMOSFETs

M.C. Sun; Min-Su Kim; J.-H. Ku; Kwan-Jong Roh; C.S. Kim; S.P. Youn; S.-W. Jung; S. Choi; N.I. Lee; Hyuk Kang; Kwang Pyuk Suh

For sub-50 nm device application, Self-Aligned siLICIDE (SALICIDE) process by NiTa alloy has been developed for the first time. Use of NiTa-alloy makes nickel silicide on 50 nm gate thermally-robust up to 600/spl deg/C during device fabrication. NiTa SALICIDE process can also achieve excellent value and distribution of sheet resistance on 30 nm gate as well as low junction leakage current compared to Co SALICIDE. Furthermore, the drive current of PMOS is greatly increased. As a result, high-performance 90 nm MOSFETs is successfully integrated with NiTa SALICIDE process.


international conference on advanced thermal processing of semiconductors | 2004

Effect of a noble annealing system on nickel silicide formation

Sug-Woo Jung; Hyun-Su Kim; Eun-ji Jung; Seong-hwee Cheong; Jong-Ho Yun; Kwan-Jong Roh; Ja-hum Ku; Gil-heyun Choi; Sung-Tae Kim; U-In Chung; Joo-Tae Moon; Byung-Il Ryu

We have investigated the formation of NiSi dependence on three types of annealing systems: annealing systems-I, -II, and -III. The annealing system-I transfers heat by radiation from tungsten halogen lamps in a N2 atmosphere to the wafer and the annealing system-II by conduction from a heated hot plate in vacuum to the wafer. On the other hand, annealing system-III uses a combination of convective and gas phase conductive heat transfer in a N2 atmosphere for wafer heating. Smooth surface and interface morphologies and good electrical properties were obtained for NiSi layers formed using annealing system-III. The wafer heat transfer mechanism from the heat source to wafer is shown to influence the morphological and electrical properties of NiSi


Archive | 2004

Methods of fabricating a semiconductor device having MOS transistor with strained channel

Min-Chul Sun; Ja-hum Ku; Sug-Woo Jung; Sun-pil Youn; Min-Joo Kim; Kwan-Jong Roh


Archive | 2004

Nickel salicide processes and methods of fabricating semiconductor devices using the same

Minjoo Kim; Ja-hum Ku; Min-Chul Sun; Kwan-Jong Roh


Archive | 2003

Nickel alloy salicide transistor structure and method for manufacturing same

Ja-hum Ku; Kwan-Jong Roh; Min-Chul Sun; Minjoo Kim


Archive | 2004

Nickel salicide process with reduced dopant deactivation

Ja-hum Ku; Kwan-Jong Roh; Min-Chul Sun; Minjoo Kim


Archive | 2003

Nickel alloy salicide process, method for manufacturing semiconductor device using the same, nickel alloy silicide film formed therefrom and semiconductor device manufactured by using the same

Jikin Gu; Minjoo Kim; Kwan-Jong Roh; Min-Chul Sun; 滋欽 具; 官鍾 盧; ▲ミン▼▲ジュ▼ 金


Archive | 2003

Method for fabricating semiconductor device using a nickel salicide process

Min-Chul San; Ja-hum Ku; Chul-Sung Kim; Kwan-Jong Roh; Min-Joo Kim


Archive | 2006

Salicide process and method of fabricating semiconductor device using the same

Sug-Woo Jung; Gil-heyun Choi; Jong-Ho Yun; Kwan-Jong Roh; Eun-ji Jung; Hyun-Su Kim


Archive | 2005

Semiconductor device having self-aligned silicide layer and method thereof

Min-Chul Sun; Ja-hum Ku; Sug-Woo Jung; Sung-Kee Han; Minjoo Kim; Kwan-Jong Roh

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