Jacek Korec

A new concept for high-voltage SOI devices

The concept for a design of high-voltage SOI-devices presented in this paper can be easily incorporated in standard silicon direct bonding (SDB) technology and enables a fabrication of lateral devices with breakdown voltages of more than 6OOV in 2-10pm thick SO1 layers. For such devices, the dependences of the breakdown voltage on the silicon layer thickness, on the doping concentration, and on the buried oxide thickness are discussed.

Trench-IGBTs with integrated diverter structures

Improved trench-IGBT structures are proposed and discussed in this paper by introducing a p/sup +/-diverter region at the bottom of the trench. This improves the reliability of the device by relaxing the electrical field at the corner of the trench and diverts holes from entering the p-base region during forward conduction and, what is more important, during switching. The performed numerical analysis for structures with a diverter connected to the cathode either via a linear resistor or a p-n diode shows, that the device with a diode diverter exhibits a significant improvement of the device performance as compared with the conventional trench-IGBT. The most important result is the excellent safe operating area of the proposed device.

Investigation of static and dynamic characteristics of SOI-LDMOSFETs passivated with semi-insulating layers

Lateral 600-V DMOSFETs on SOI (silicon-on-insulator) substrates have been used as test devices to compare conventional oxide passivation with a passivation system consisting of oxide and an additional semiresistive layer (SIPOS or Si/sub x/N/sub y/). The effect of the passivation on the breakdown voltage and the dependence of the reverse I-V characteristic on the passivation system, temperature, and substrate voltage are discussed. Both semiresistive layers, SIPOS and Si/sub x/N/sub y/, are shown to reduce the backgate effect in the breakdown voltage and are therefore superior to the conventional oxide passivation. The level of the reverse current is not increased by the parasitic current through the semiresistive layer but is significantly affected by a similar backgate effect. No indication of a degradation of the dynamic performance of the lateral MOSFETs by passivation with a stack of an oxide and a capping semiresistive layer was found.<<ETX>>

Silicon-on-insulator technology for high-temperature, smart-power applications

Abstract The motivation to develop high-temperature resistant smart-power products and the impact of silicon-on-insulator (SOI) technology are discussed. The electrical and thermal behaviour of devices on SOI-substrates is illustrated, with examples, showing that smart-power integrated circuits can be designed for operation at chip temperatures up to 200 °C allowing the use of low-cost packaging techniques at ambient temperatures up to 130 °C. Some reliability issues limiting a broader application of smart power devices at high temperature at the present time are also considered.

Comparison of lateral EST and IGBT devices on SOI substrates

Lateral IGBTs (insulated-gate bipolar transistors) and ESTs (emitter-switched thyristors) on SOI (silicon-on-insulator) substrates are compared experimentally and by computer simulation. Experimental and calculated forward characteristics are presented. The influence of some device parameters on forward and blocking properties is discussed. Turn-off characteristics of both structures are presented for fabricated devices and compared to computer calculations. LESTs in SOI substrates are shown to have lower forward voltage drop or to switch faster than equivalent lateral IGBTs, depending on carrier lifetimes, which can be adjusted, for example, by electron irradiation. An advantageous LEST behavior was demonstrated by numerical simulation for comparatively small devices with small breakdown voltages ( approximately=220 V), and this advantage is expected to increase for larger devices with larger breakdown voltages.<<ETX>>

A versatile linkage device for high-voltage ICs

A device operating as an integrated voltage-source for power supply and as a controllable current-source for level shifting in high-voltage integrated circuits has been designed and tested experimentally. Two-dimensional modelling results are in good agreement with the measurements. A SPICE macro-model useful for circuit design is presented and applications for smart power design are discussed.