Jack I. Raffel

A monolithic Hough transform processor based on restructurable VLSI

The implementation of a Hough transform processor using a wafer-scale-integration technology, restructurable VLSI circuit is described. The Hough transform is typically used as a grouping operation in an image processing sequence. The transform discussed here groups pixels in order to extract linear features. This calculation is realized with a wafer-scale processor that allows a complete line extraction system to be integrated on a single PC board. Also discussed is the use of the CAD tools that allowed this processor to be realized without incurring silicon layout and processing overhead. >

Magnetic Film Memory Design

Thin magnetic films of permalloy have characteristics ideal for high-speed digital storage. A simple rotational model modified to include the effects of wall switching and dispersion of the preferred direction of magnetization provides a basis for describing properties of engineering interest. A selection system has been chosen which allows great latitude in film uniformity. Production of films with magnetic properties uniform to within ± 10 per cent is readily achieved. Specifications for operation in a destructive mode can easily be met by existing film arrays; the nondestructive mode is considerably more stringent unless very small signals can be tolerated. The first film memory has been in reliable operation since the summer of 1959. It has 32 ten-bit words and has been operated with a minimum cycle time of 0.4 , μsec. Higher speed and larger capacities will require higher bit densities and improved techniques to minimize undesirable coupling between drive and sense lines. The use of 10 × 60 mil rectangles, balanced sense windings, and longer words will hopefully permit memories of about 200,000 bits with cycle time under 0.2 μsec.

Restructurable VLSI-a demonstrated wafer-scale technology

Restructurable VLSI (RVLSI) is an approach to wafer-scale integration which has been demonstrated by building six different monolithic silicon, wafer-scale chips for signal processing applications. It is based on the implementation of redundancy by laser microwelding on a finished, tested, packaged wafer. The concept of RVLSI is discussed, the chips built to data are reviewed, and some of the major issues are introduced. Three other papers describe in more detail the laser technology, the software created to design, test, and restructure these systems, some of the knowledge acquired in designing and building the first six circuit types, and the current application of the techniques to new, much more complex designs.<<ETX>>

Operating Characteristics of a Thin Film Memory

An experimental prototype memory with 32 ten bit words has been designed, built, and tested. Circular spots 116 in. in diameter about 600 A thick are used. These are evaporated on two pieces of glass each comprising a 16×16 spot array. An operating cycle time of less than one‐half microsecond appears possible.The circuitry for driving and sensing is transistorized and the memory uses external register selection from a core‐diode matrix. Word selection is provided by a transverse field, and a digit winding conditions the information written by applying a longitudinal field in the “one” or “zero” direction.Extension to sizes of the order of 1000 words is planned using these techniques. The memory constructed here will soon be installed in the control element of the TX‐2 computer.

A wafer-scale digital integrator using restructurable VSLI

Wafer-scale integration has been demonstrated by fabricating a digital integrator on a monolithic 20-cm2silicon chip, the first laser-restructured digital logic system. Large-area integration is accomplished by laser programming of metal interconnect for defect avoidance. This paper describes the technology for laser welding and cutting, the design methodology and CAD tools developed for wafer-scale integration, and the integrator itself.

Laser Restructurable Technology and Design

The Restructurable VLSI project at MIT Lincoln Laboratory has developed a design methodology, new technology, and CAD tools for WSI. Six wafer scale systems have been fabricated and three of much larger size are being designed. Figure 1 shows one of these packaged WS circuits. The accomplishments and current research status of this project, which was conceived in 1979 [1], are described in this chapter.

Laser‐formed connections using polyimide

Electrical connections have been formed in a new lateral link structure which uses polyimide in the gap between, and overlapping, two aluminum electrodes. An argon ion laser, with a pulse width of 1 ms and power levels of about 2 W, was used to locally graphitize the polyimide. One kilohm connections were formed reliably in links ranging in width between 4 and 15 μm and gap length between 2 and 5 μm. This technique is the simplest yet proposed for restructuring the connections on an integrated circuit, after fabrication and test, in order to incorporate redundancy for yield improvement.

A novel double-metal structure for voltage-programmable links

A novel metal-insulator-metal (MIM) structure has been developed for use in field-programmable gate arrays (FPGAs) as a voltage-programmable link (VPL). The present structure relies on a combination of a refractory metal and aluminum as the lower electrode, and aluminum alone as the top electrode. The insulator, prepared by means of plasma-enhanced chemical vapor deposition, comprises a sandwich of nearly stoichiometric silicon dioxide interposed between two layers of silicon-rich silicon nitride. This MIM structure has displayed characteristics desirable for use in the emerging FPGA technology.<<ETX>>

A self-organizing neural net chip

A circuit has been designed and fabricated which implements a self-organizing algorithm proposed by T. Kohonen (1984). It uses a competitive learning process which modifies weights such that similar input feature vectors are clustered into distinct classes. This network learns without supervision. Matching is accomplished by computing the squared Euclidean distance at each node between the input and the current weight vector. Connections to each node are implemented with multiplying D/A converters. The weights are stored in dynamic RAM registers at each connection. The design minimizes circuit area by using unary encoding in the weight representation to permit the use of shift operations in the adaption process and by sharing the circuits used in weight adaptation and the activation computations.<<ETX>>

A novel metal-insulator-metal structure for field-programmable devices

A metal-insulator-metal (MIM) capacitor structure has been developed for use in field-programmable gate arrays (FPGAs) as a voltage-programmable link (VPL). The structure relies on a combination of a refractory metal and aluminum as the lower electrode, and either a similar combination or aluminum alone as the top electrode. The insulator is prepared by means of plasma-enhanced chemical vapor deposition (PECVD). It comprises a sandwich of nearly stoichiometric silicon dioxide interposed between two like layers of silicon-rich silicon nitride. The structure has displayed characteristics desirable for use in emerging FPGA technology, including high density, low on-resistance, reduced capacitance, and low programming voltage. >