Peter W. Wyatt

A wafer-scale 3-D circuit integration technology

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described

MEMS microswitches for reconfigurable microwave circuitry

The performance is reported for a new microelectromechanical structure (MEMS) cantilever microswitch. We report on both dc- and capacitively-contacted microswitches. The dc-contacted microswitches have contact resistance of less than 1 /spl Omega/, and the RF loss of the switch up to 40 GHz in the closed position is 0.1-0.2 dB. Capacitively-contacted switches have an impedance ratio of 141:1 from the open to closed state and in the closed position have a series capacitance of 1.2 pF. The capacitively-contacted switches have been measured up to 40 GHz with S/sub 22/ less than -0.7 dB across the 5-40 GHz band.

High-speed Schottky-barrier pMOSFET with f/sub T/=280 GHz

High-speed results on sub-30-nm gate length pMOSFETs with platinum silicide Schottky-barrier source and drain are reported. With inherently low series resistance and high drive current, these deeply scaled transistors are promising for high-speed analog applications. The fabrication process simplicity is compelling with no implants required. A sub-30-nm gate length pMOSFET exhibited a cutoff frequency of 280 GHz, which is the highest reported to date for a silicon MOS transistor. Off-state leakage current can be easily controlled by augmenting the Schottky barrier height with an optional blanket As implant. Using this approach, good digital performance was also demonstrated.

Engineering polycrystalline Ni films to improve thickness uniformity of the chemical-vapor-deposition-grown graphene films

It has been shown that few-layer graphene films can be grown by atmospheric chemical vapor deposition using deposited Ni thin films on SiO(2)/Si substrates. In this paper we report the correlation between the thickness variations of the graphene film with the grain size of the Ni film. Further investigations were carried out to increase the grain size of a polycrystalline nickel film. It was found that the minimization of the internal stress not only promotes the growth of the grains with (111) orientation in the Ni film, but it also increases their grain size. Different types of SiO(2) substrates also affect the grain size development. Based upon these observations, an annealing method was used to promote large grain growth while maintaining the continuity of the nickel film. Graphene films grown from Ni films with large versus small grains were compared for confirmation.

FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics

Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate.

Restructurable VLSI-a demonstrated wafer-scale technology

Restructurable VLSI (RVLSI) is an approach to wafer-scale integration which has been demonstrated by building six different monolithic silicon, wafer-scale chips for signal processing applications. It is based on the implementation of redundancy by laser microwelding on a finished, tested, packaged wafer. The concept of RVLSI is discussed, the chips built to data are reviewed, and some of the major issues are introduced. Three other papers describe in more detail the laser technology, the software created to design, test, and restructure these systems, some of the knowledge acquired in designing and building the first six circuit types, and the current application of the techniques to new, much more complex designs.<<ETX>>

Reoxidized nitrided oxide for radiation-hardened MOS devices

A 37-nm reoxidized nitrided oxide has been developed that exhibits zero interface-state density increase, less than -1.5-V midgap voltage shift, and less than 5% degradation in inversion layer mobility after irradiation to 50 Mrad(SiO/sub 2/) with +or-5 V applied to the gate. Bias annealing studies demonstrate that midgap voltage-shift recovery is more rapid than in conventional hardened oxide, indicating that these dielectrics will compare even more favorably with hard oxide at lower dose rates. The experiments also indicate that the density of hole traps in reoxidized nitrided oxide is sharply peaked at both interfaces and that the same species of trap dominates trapping at both interfaces. >

A wafer-scale digital integrator using restructurable VSLI

Wafer-scale integration has been demonstrated by fabricating a digital integrator on a monolithic 20-cm2silicon chip, the first laser-restructured digital logic system. Large-area integration is accomplished by laser programming of metal interconnect for defect avoidance. This paper describes the technology for laser welding and cutting, the design methodology and CAD tools developed for wafer-scale integration, and the integrator itself.

An SOI-based three-dimensional integrated circuit technology

Three-dimensional integrated circuits (3D-ICs) composed of active circuit layers that are vertically stacked and interconnected are expected to lead to improved logic devices, memories, CPUs, and photosensors (Akasaka, 1986). These circuits require high-density vertical interconnections (3D vias) comparable in aspect ratio to present multilevel vias (Reber and Tielert, 1996). We have constructed and tested 3D ring oscillators and fully parallel 64/spl times/64 active pixel sensors using a 3D assembly technology which utilizes SOI wafers to achieve stacking of multiple circuit layers and unrestricted placement of dense 3D vias.

On the body-source built-in potential lowering of SOI MOSFETs

This letter provides a viewpoint for the characterization of state-of-the-art thin film silicon-on-insulator (SOI) MOSFETs. Based on body-source built-in potential lowering, the degree of full depletion can be quantified. In addition to serving as a measure of the floating-body behavior of SOI devices, the concept also enables the consolidation of partial-depletion (PD) and full-depletion (FD) SOI compact models. This consolidation of compact models together with the trend of coexistence of PD/FD devices in a single chip has become one of the greatest challenges in the scaling of SOI CMOS.