Antonio M. Soares

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 /spl mu/m/spl times/2 /spl mu/m/spl times/7.5 /spl mu/m 3D via to connect a deep depletion, 100% fill-factor photodiode layer to a fully depleted SOI CMOS readout circuit layer. Pixel operability exceeds 99.9%, and the detector has a dark current of <3 nA/cm/sup 2/ and pixel responsivity of /spl sim/9 /spl mu/V/e at room temperature.

Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers

A 64times64 laser-radar (ladar) detector array with 50mum pixel size measures the arrival times of single photons using Geiger-mode avalanche photodiodes (APD). A 3-tier structure with active devices on each tier is used with 227 transistors, six 3D vias and an APD in each pixel. A 9b pseudorandom counter in the pixel measures time. Initial imagery shows 2ns time quantization

A novel metal-insulator-metal structure for field-programmable devices

A metal-insulator-metal (MIM) capacitor structure has been developed for use in field-programmable gate arrays (FPGAs) as a voltage-programmable link (VPL). The structure relies on a combination of a refractory metal and aluminum as the lower electrode, and either a similar combination or aluminum alone as the top electrode. The insulator is prepared by means of plasma-enhanced chemical vapor deposition (PECVD). It comprises a sandwich of nearly stoichiometric silicon dioxide interposed between two like layers of silicon-rich silicon nitride. The structure has displayed characteristics desirable for use in emerging FPGA technology, including high density, low on-resistance, reduced capacitance, and low programming voltage. >

High frequency performance of a fully depleted 0.25-/spl mu/m SOI CMOS technology

A fully depleted (FD) 0.25-/spl mu/m silicon-on-insulator (SOI) CMOS process technology has been developed and established at Lincoln Laboratory. Here we describe the FDSOI process technology, report the high frequency performance of 0.25-/spl mu/m n- and p-channel MOSFETs and digital and analog circuits, and predict the performance of the FDSOI technology scaled to 0.1-/spl mu/m gate lengths.

The Lincoln programmable image-processing wafer

The Programmable Image Processor is a laser-restructurable, wafer-scale device fabricated on a 125-mm wafer using an n-well CMOS process with 2.0 micrometer gates. Yield projections indicate that one wafer has enough devices to construct an array of 16 SIMD-programmable processors and 25 shared memories. The memory array can store two images each 128-by-128 pixels. One run of wafers has been fabricated, and these wafers were undergoing testing and restructuring at the time of publication.<<ETX>>

Performance of a low power fully-depleted deep submicron SOI technology and its extension to 0.15 /spl mu/m

Lincoln Laboratory has developed a fully-depleted silicon-on-insulator (SOI) technology to build integrated circuits designed for very low power operation and fabricated at the limits of optical lithography. A 0.25 /spl mu/m (drawn gate length) fully-depleted SOI CMOS process technology was established using 248-nm optical lithography for initial process demonstrations, and to identify nonlithographic process integration pinch points and SOI material related issues. Design rules and SPICE parameters have been issued for the 0.25 /spl mu/m technology and a multi-project chip set assembled. The process technology has been adapted to Lincolns 193-nm step-and-scan tool to fabricate O.2 /spl mu/m circuits and provide the first application of 193-nm lithography to a complete CMOS process. This paper describes the performance characteristics of the technology and the enhancements necessary to extend it to 0.15 /spl mu/m.

Design criteria for a fully depleted-0.1 /spl mu/m SOI technology

A sub-0.25 /spl mu/m fully depleted silicon-on-insulator (FDSOI) technology has been developed and fully scaled ring oscillators fabricated using 193-nm lithography. This technology is being extended by incorporating phase shift techniques with 193-nm lithography to fabricate polysilicon gates with 0.1 /spl mu/m drawn channel lengths. The purpose of this paper is to define the process and design requirements for a fully depleted, 0.1 /spl mu/m SOI technology and predict the performance characteristics of 0.1 /spl mu/m ring oscillators.

Robust subthreshold level conversion

We describe a robust level converter that is capable of converting up to 1.2V from a subthreshold input voltage of 60mV. Measurement results are given for test circuits fabricated in a 90nm FDSOI subthreshold optimized process.

Total dose performance of conventional static and dynamic circuits in a radhard 0.18-/spl mu/m FDSOI process

Static and dynamic circuits were fabricated in the MIT-LL 0.18-/spl mu/m FDSOI CMOS process, and exhibited a high tolerance to total dose radiation up to 1 Mrad (SiO/sub 2/). Circuits were designed using conventional design rules and layout techniques, i.e., they are not radhard-by-design. Hardening was done at the circuit fabrication level using process enhancements. These are the first circuit-level hardness results reported to date for these new enhancements.