Robert Berger

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 /spl mu/m/spl times/2 /spl mu/m/spl times/7.5 /spl mu/m 3D via to connect a deep depletion, 100% fill-factor photodiode layer to a fully depleted SOI CMOS readout circuit layer. Pixel operability exceeds 99.9%, and the detector has a dark current of <3 nA/cm/sup 2/ and pixel responsivity of /spl sim/9 /spl mu/V/e at room temperature.

Design approaches for digitally dominated active pixel sensors: leveraging Moore's Law scaling in focal plane readout design

Although CMOS technology scaling has provided tremendous power and circuit density benefits for innumerable applications, focal plane array (FPA) readouts have largely been left behind due to dynamic range and signal-to-noise considerations. However, if an appropriate pixel front end can be constructed to interface with a mostly digital pixel, it is possible to develop sensor architectures for which performance scales favorably with advancing technology nodes. Although the front-end design must be optimized to interface with a particular detector, the dominant back end architecture provides considerable potential for design reuse. In this work, digitally dominated long wave infrared (LWIR) active pixel sensors with cutoff wavelengths between 9 and 14.5 μm are demonstrated. Two ROIC designs are discussed, each fabricated in a 90-nm digital CMOS process and implementing a 256 x 256 pixel array on a 30-μm pitch. In one of the implemented designs, the feasibility of implementing a 15-μm pixel pitch FPA with a 500 million electron effective well depth, less than 0.5% non-linearity in the target range and a measured NEdT of less than 50 mK at f/4 and 60 K is demonstrated. Simple on-FPA signal processing allows for a much reduced readout bandwidth requirement with these architectures. To demonstrate the potential for commonality that is offered by a digitally dominated architecture, this LWIR sensor design is compared and contrasted with other digital focal plane architectures. Opportunities and challenges for application of this approach to various detector technologies, optical wavelength ranges and systems are discussed.

Design and testing of an all-digital readout integrated circuit for infrared focal plane arrays

The digital focal plane array (DFPA) project demonstrates the enabling technologies necessary to build readout integrated circuits for very large infrared focal plane arrays (IR FPAs). Large and fast FPAs are needed for a new class of spectrally diverse sensors. Because of the requirement for high-resolution (low noise) sampling, and because of the sample rate needed for rapid acquisition of high-resolution spectra, it is highly desirable to perform analog-to-digital (A/D) conversion right at the pixel level. A dedicated A/D converter located under every pixel in a one-million-plus element array, and all-digital readout integrated circuits will enable multi- and hyper-spectral imaging systems with unprecedented spatial and spectral resolution and wide area coverage. DFPAs provide similar benefits to standard IR imaging systems as well. We have addressed the key enabling technologies for realizing the DFPA architecture in this work. Our effort concentrated on demonstrating a 60-micron footprint, 14-bit A/D converter and 2.5 Gbps, 16:1 digital multiplexer, the most basic components of the sensor. The silicon test chip was fabricated in a 0.18-micron CMOS process, and was designed to operate with HgxCd1-xTe detectors at cryogenic temperatures. Two A/D designs, one using static logic and one using dynamic logic, were built and tested for performance and power dissipation. Structures for evaluating the bit-error-rate of the multiplexer on-chip and through a differential output driver were implemented for a complete performance assessment. A unique IC probe card with fixtures to mount into an evacuated, closed-cycle helium dewar were also designed for testing up to 2.5 Gbps at temperatures as low as 50 K.

High frequency performance of a fully depleted 0.25-/spl mu/m SOI CMOS technology

A fully depleted (FD) 0.25-/spl mu/m silicon-on-insulator (SOI) CMOS process technology has been developed and established at Lincoln Laboratory. Here we describe the FDSOI process technology, report the high frequency performance of 0.25-/spl mu/m n- and p-channel MOSFETs and digital and analog circuits, and predict the performance of the FDSOI technology scaled to 0.1-/spl mu/m gate lengths.

A laser-programmable multichip module on silicon

A laser-programmable substrate for multichip modules comprises a silicon substrate with a dense, predefined array of pads, tracks and links. A pattern of wiring connecting some of the pads is formed with a laser. Integrated circuit chips are mounted on the substrate, and the chip pads are wire-bonded to the substrate pads. East-west tracks are on the second level of metal, and north-south tracks on the first level. Power, ground, and signals share the tracks on the two metal layers. There is an array of 258-by-258 pads on a 200- mu m pitch, and there are three signal tracks, one power track, and one ground track between any two adjacent pads. Links consist of a silicon nitride layer sandwiched between the two metal layers. When a laser pulse of the correct power and duration is directed to the link region, the metal and nitride fuse to form a conductive vertical path, with a resistance typically two ohms.<<ETX>>

The Lincoln programmable image-processing wafer

The Programmable Image Processor is a laser-restructurable, wafer-scale device fabricated on a 125-mm wafer using an n-well CMOS process with 2.0 micrometer gates. Yield projections indicate that one wafer has enough devices to construct an array of 16 SIMD-programmable processors and 25 shared memories. The memory array can store two images each 128-by-128 pixels. One run of wafers has been fabricated, and these wafers were undergoing testing and restructuring at the time of publication.<<ETX>>

Lincoln Laboratory high-speed solid-state imager technology

Massachusetts Institute of Technology, Lincoln Laboratory (MIT LL) has been developing both continuous and burst solid-state focal-plane-array technology for a variety of high-speed imaging applications. For continuous imaging, a 128 × 128-pixel charge coupled device (CCD) has been fabricated with multiple output ports for operating rates greater than 10,000 frames per second with readout noise of less than 10 e- rms. An electronic shutter has been integrated into the pixels of the back-illuminated (BI) CCD imagers that give snapshot exposure times of less than 10 ns. For burst imaging, a 5 cm × 5 cm, 512 × 512-element, multi-frame CCD imager that collects four sequential image frames at megahertz rates has been developed for the Los Alamos National Laboratory Dual Axis Radiographic Hydrodynamic Test (DARHT) facility. To operate at fast frame rates with high sensitivity, the imager uses the same electronic shutter technology as the continuously framing 128 × 128 CCD imager. The design concept and test results are described for the burst-frame-rate imager. Also discussed is an evolving solid-state imager technology that has interesting characteristics for creating large-format x-ray detectors with ultra-short exposure times (100 to 300 ps). The detector will consist of CMOS readouts for high speed sampling (tens of picoseconds transistor switching times) that are bump bonded to deep-depletion silicon photodiodes. A 64 × 64-pixel CMOS test chip has been designed, fabricated and characterized to investigate the feasibility of making large-format detectors with short, simultaneous exposure times.

Saturable Shielding‐A Technique for Nonlinear Coupling in Magnetic Circuits

If a magnetic film (the shield) with transverse saturation demagnetizing field Hd and anisotropy field Hk is placed in a transverse field below saturation strength (Hd+Hk), it experiences a net field less than Hk. A second film (the storage film), when placed on top of the first, will experience the same net field. If the anisotropy field of the storage film is much greater than that of the shield, the magnetization of the storage film undergoes a negligible rotation for all applied fields below Hd+Hk. Once the shield has saturated, any further increase in field is applied directly to storage film. The resulting plot of the net field at the storage film versus applied field shows a symmetrical offset threshold of approximate magnitude Hd. Control of the shield geometry provides a means for adjusting this threshold.To investigate the shielding effect, two experiments were performed. The first used a 0.5‐in.‐wide Supermalloy tape to approximate an ideal shield and measured net field at its center line as a ...

Gigahertz (GHz) hard x-ray imaging using fast scintillators

Gigahertz (GHz) imaging technology will be needed at high-luminosity X-ray and charged particle sources. It is plausible to combine fast scintillators with the latest picosecond detectors and GHz electronics for multi-frame hard Xray imaging and achieve an inter-frame time of less than 10 ns. The time responses and light yield of LYSO, LaBr3, BaF2 and ZnO are measured using an MCP-PMT detector. Zinc Oxide (ZnO) is an attractive material for fast hard X-ray imaging based on GEANT4 simulations and previous studies, but the measured light yield from the samples is much lower than expected.