Jack Lau

A 900 MHz CMOS balanced harmonic mixer for direct conversion receivers

A 900 MHz balanced harmonic mixer for direct conversion receivers is fabricated in a 0.35 /spl mu/m standard digital CMOS process. The self-mixing-induced DC offset is about 44 dB lower than that of the conventional mixer. The input referred offset is reduced to the noise level. Specific techniques on flicker noise reduction are also discussed. At 3 V power supply and -15.4 dBm LO power, it achieves 13 dB conversion gain, 24.5 dB noise figure at 10 kHz, -10 dBm third-order input intercept point and +36 dBm second-order input intercept point. The total power consumption is about 5 mW.

A wide tuning range gated varactor

A wide tuning range gated varactor for radio frequency (RF) applications is described in this paper. The gated varactor is a three-terminal device. The third terminal helps achieve an improved tuning range. The measured tuning range of the varactor exceeds /spl plusmn/50%. The new device can be implemented with a standard CMOS process without any post-processing. A 2 GHz prototype voltage-controlled oscillator (VCO) is implemented using the new varactor in a 0.35-/spl mu/m CMOS process. The VCO achieved a sensitivity of 220 MHz/V.

Experimental results and modeling of noise coupling in a lightly doped substrate

While an in-depth experimental study of substrate noise coupling in an epi process has been reported, most research into substrate coupling in lightly doped bulk wafers has been limited to simulations without experimental confirmation. This work presents experimental noise coupling data for a lightly doped substrate, along with corresponding simulation results obtained using a compact model of the substrate. The results of this work provide a general understanding of noise coupling in lightly doped substrates and emphasize the layout dependence of such noise. Without an efficient simulation capability utilizing a compact model of the substrate, it is extremely difficult to predict how noise will couple to a circuit node.

Considerations on applying OFDM in a highly efficient power amplifier

A major obstacle in applying orthogonal frequency-division multiplexing (OFDM) in wireless local networks is the need for a highly linear and efficient radio frequency power amplifier. The strong fluctuated envelope of an OFDM signal makes it difficult to build this kind of power amplifier. In this paper, we consider the use of the envelope elimination and restoration method for OFDM power amplification and evaluate its performance tradeoffs. The results are compared to the performance of a linear power amplifier with different power backoffs. In addition, as the envelope of an OFDM signal is concentrated at low level, the average output power is low when a low supply voltage power amplifier is used. Simulation is done to show that the signal power (or signal-to-noise ratio for fixed noise level) can be traded off with clipping level for optimum bit-error-rate without increasing power supply voltage.

SPICE simulation and tradeoffs of CMOS LNA performance with source-degeneration inductor

In this brief, we study the tradeoffs of CMOS low noise amplifiers using source-degeneration inductor with both experimental data and simulation data. SPICE models based on the quasistatic (QS) assumption ignores the channel resistance and leads designers to overly rely on source-degeneration inductance. The non-QS model is much better. Source inductor adversely affects noise and gain. The parasitic capacitance at the gate imposes additional challenges for matching.

A physical thermal noise model for SOI MOSFET

The recent progress in SOI technology necessitates an accurate thermal noise model for wide-band SOI analog IC design. In this paper a physical-based thermal noise model is proposed for floating-body SOI MOSFET operated in strong inversion regime and verified by the experimental data. In the model, both the lattice temperature (unique to SOI due to the buried oxide) and the carrier temperature (significant for short-channel device in saturation region) are considered. The model agrees well with the experimental data.

A three-terminal SOI gated varactor for RF applications

This paper presents a new CMOS compatible SOI gated varactor for use in RF ICs. With its additional third terminal, the device offers an exceptional large tuning range and a good quality factor. The result of the MEDICI simulation of the structure of the varactor has been confirmed with measured data. A VCO circuit that can potentially exploit the three-terminal property is also reported.

Experimental results and simulation of substrate noise coupling via planar spiral inductor in RF ICs

While previous studies on substrate coupling focused mostly on noise induced through drain-bulk capacitance, substrate coupling from planar spiral inductors at radio frequency via the oxide capacitance have not been reported. This paper presents experimental data and simulation results for inductor-induced noise in the substrate. Noise coupling from conventional and hollow inductors via the substrate to P+ diffusions with and without guard rings were also examined. A compact model of the inductor and substrate that can accurately match the measured inductor-induced noise is then derived. Using the inductor-substrate model, we investigated the effectiveness of various guard rings configurations to reducing substrate noise coupling, the trade-off between noise coupling and self-inductance, and the coupling of noise from the inductor of a tuned RF amplifier.

Modelling of split-drain magnetic field-effect transistor (MAGFET)

Abstract By simply splitting the drain of a conventional MOS transistor into two, we can convert the transistor into a magnetic sensor. The ease of integrating split-drain magnetic field-effect transistors (MAGFETs) in conventional CMOS technology and the potential of sensing small magnetic fields have fascinated many researchers. Yet many parameters, such as the maximum sensitivity and biasing dependence of the device, are not yet known. In this paper, we describe a model for the split-drain MAGFET. The model shows that the sensitivity of the sensor is primarily a function of the roll-off of the induced Hall potential in the channel and that the contribution due to channel inversion charge redistribution is very minor. The model also shows that the magnetic-field signal in terms of ΔId/Id is insensitive to geometry, linear to magnetic-field strength and affected by the gap between the two drains. Furthermore, we show that the sensitivity is typically limited by the Hall mobility, insensitive to operating regions and attributed to saturation voltage shifts in the saturation region. A maximum sensitivity of less than 5.8% T−1 is predicted. The development of the model is assisted by computer simulations and verified by experimental results.

A 930 MHz CMOS DC-offset-free direct-conversion 4-FSK receiver

Although direct-conversion has potential for high integration and low cost, it is plagued by issues ranging from DC offset to flicker noise. While most recent integrated single-chip direct conversion receivers concentrate on wideband applications where flicker noise and DC offset can be filtered out without affecting performance, focus here is on a narrow-band application using CMOS technologies. This effort is to fully integrate RF and baseband circuitry for a narrow-band application such as a high-speed pager, which uses a 4-FSK modulation scheme. The receiver overcomes the problem using a harmonic mixing and a DC-offset cancellation.