Cuong T. Nguyen

Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors

The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented.

Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's

The threshold voltage, V/sub th/, of fully depleted silicon-on-insulator (FDSOI) MOSFET with effective channel lengths down to the deep-submicrometer range has been investigated. We use a simple quasi-two-dimensional model to describe the V/sub th/ roll-off and drain voltage dependence. The shift in threshold voltage is similar to that in the bulk. However, threshold voltage roll-off in FDSOI is less than that in the bulk for the same effective channel length, as predicted by a shorter characteristic length l in FDSOI. Furthermore, /spl Delta/V/sub th/ is independent of back-gate bias in FDSOI MOSFET. The proposed model retains accuracy because it does not assume a priori charge partitioning or constant surface potential. Also it is simple in functional form and hence computationally efficient. Using our model, V/sub th/ design space for Deep-Submicrometer FDSOI MOSFET is obtained. Excellent correlation between the predicted V/sub th/ design space and previously reported two-dimensional numerical simulations using MINIMOS5 is obtained. >

Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFETs for high performance analog and mixed signal circuits

This paper compared the performance of conventional fully depleted (FD) SOI MOSFETs and body-grounded nonfully depleted (NFD) SOI MOSFETs for analog applications, A new low-barrier body-contact (LBBC) technology has been developed to provide effective body contact. Experimental results show that the NFD MOSFETs with LBBC structure give one order of magnitude higher output resistance, significantly lower flicker noise, improved subthreshold characteristics, and minimal threshold voltage variation compared with conventional FD SOI MOSFETs. The device characteristics of the LBBC MOSFETs are more desirable for fabricating high performance analog or mixed analog/digital CMOS circuits. >

Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's

Fully depleted SOI MOSFETs include an inherent parasitic lateral bipolar structure with a floating base. We present here the first complete physically based explanation of the bipolar gain mechanism, and its dependence on bias and technological parameters. A simple, one-dimensional physical model, with no fitting parameters, is constructed, and is shown to agree well with simulations and measurements performed on a new type of SOI MOSFET structure. It is shown that parameters which affect the gain, such as SOI layer thickness, body doping concentration and gate and drain voltages, do so primarily by affecting the concentration of holes in the body region. Thus, current gain falls dramatically with increasing drain voltage due to the associated impact ionization driven increase in the hole concentration. Gummel plots of this parasitic bipolar indicate an apparent ideality factor of 0.5 for the hole current, due to the body hole concentrations dependence on drain voltage. >

Spatial temperature profiles due to nonuniform self-heating in LDMOS's in thin SOI

Temperature profiles resulting from self-heating in SOI-LDMOS devices with uniformly doped and linearly graded drift regions were measured using a resistance thermometry technique. Two-dimensional electrothermal device simulations were performed and the results agreed with the experiments. Because of the different power dissipation profiles, RESURF devices with a uniformly doped drift region assume a fairly uniform temperature distribution while devices with a linearly graded drift region have a much higher temperature rise near the source than the drain. This local hot spot near the source raises reliability issues in device design.

Polished TFT's: surface roughness reduction and its correlation to device performance improvement

Chemical-mechanical polishing (CMP) has been applied to the fabrication of n-channel polysilicon thin film transistors (poly-Si TFTs). Three different polishing conditions are compared: (1) polishing before; (2) polishing after; and (3) both polishing before and after the a-Si recrystallization. Devices with no polishing act as control samples. Experiments consistently reveal that devices with post-anneal polishing exhibit the best performance, Two-fold improvement of drain current is attributed to the smoother active polysilicon surface. The electrical characteristics of a post-anneal polished TFT in terms of field effect mobility /spl mu//sub FE/, threshold voltage V/sub T/, and subthreshold swing S can be further improved if hydrogenation is employed. It is also found that a large decrease in the poly-Si surface roughness leads to higher dielectric breakdown strength and improved short-channel effects. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) results are presented and correlated with electrical results.

High voltage LDMOS transistors in sub-micron SOI films

Silicon-on-insulator (SOI) LDMOS transistors with a linearly graded doping profile in the drift region have been found to exhibit both low on-resistance and high breakdown voltage. High-side operation is a problem for devices built in very thin SOI layers due to pinch-off of the drift region. This is less of a problem for devices built in thicker SOI layers. Devices built in thicker SOI films also are more tolerant of manufacturing variations and offer more predictable behaviour. Non-uniform self-heating within the drift region has been measured for the first time. A breakdown voltage of 1020 V is reported for a LDMOS transistor made in a 0.15 /spl mu/m SOI layer.

SOI MOSFET with buried body strap by wafer bonding

Although the buried oxide in the silicon-on-insulator (SOI) MOSFET makes possible higher performance circuits, it is also responsible for various floating body effects, including the kink effect, drain current transients, and history dependence of output characteristics. It is difficult to incorporate an effective contact to the body because of limitations imposed by the SOI structure. One candidate, which maintains device symmetry, is the lateral body contact. However, high lateral body resistance makes the contact effective only in narrow width devices. In this work, a buried lateral body contact in SOI is described which consists of a low-resistance polysilicon strap running under the MOSFET body along the device width. MOSFETs with effective channel length of 0.17 /spl mu/m have been fabricated incorporating this buried body strap, showing improved breakdown characteristics. Low leakage of the source and drain junctions demonstrates that the buried strap is compatible with deep submicron devices. Device modeling and analysis are used to quantify the effect of strap resistance on device performance. By accounting for the lateral resistance of the body, the model can be used to determine the maximum allowable device width, given the requirement of maintaining an adequate body contact.

Array probe card

By utilizing conventional IC processing techniques, a membrane probe card has been fabricated on a silicon wafer and its functionality demonstrated. The probe card was able to provide a very large number of probe tips in an array form, permanently fixed in the X-Y plane via a transparent, flexible membrane. The use of an electrical current pulse, instead of a mechanical scrubbing motion, to break down the interfacial oxide has been demonstrated. The contact resistance was about 5*10/sup -5/ Omega -cm/sup 2/. The new probe card offers smaller probe parasitics. The addition of the active test circuitry on the probe card would allow very high speed wafer level testing.<<ETX>>

Optimizing polysilicon thin-film transistor performance with chemical-mechanical polishing and hydrogenation

Chemical-mechanical polishing and hydrogen passivation were jointly used to improve the electrical characteristics of polycrystalline-Si thin-film transistors (poly-Si TFTs). It was found that each treatment affects the devices differently; polishing is more effective in smoothing the poly-Si/SiO/sub 2/ interface while hydrogenation is more effective in passivating the grain boundaries. Their effects are additive. Hence, optimal device performance was achieved by combining both treatments.