Mark Vesterbacka

A 14-transistor CMOS full adder with full voltage-swing nodes

We explain how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also produces a complementary XNOR output is introduced in the general full adder. The resulting full adder circuit is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes. Layouts have been made in a 0.35 /spl mu/m process for both the proposed full adder circuit and another 16-transistor full adder circuit based on pass transistors. The performance of the proposed full adder is evaluated by comparison of the simulation results obtained from HSPICE for both layouts. The two adders yield similar performance in terms of power consumption, power delay product, and propagation delay. The area is somewhat lower for the proposed adder due to the reduced device count. However, due to two feedback MOSFETs in the proposed adder that need to be ratioed, there is a higher cost in terms of design effort for the proposed adder.

A multiplexer based decoder for flash analog-to-digital converters

A decoder for flash analog-to-digital converters with short critical path, regular structure, and small area is presented. The decoder is based on 2:1 multiplexers connected as a tree. Each level of the tree divides the input thermometer scale in two and calculates one of the bits in the binary output. In comparison with the Wallace tree decoder and the folded decoder the length of the critical path is approximately reduced to one third and one half, respectively. The amount of hardware is also reduced, which is likely to translate to a power saving, compared with the Wallace tree decoder and the folded decoder.

A study of digital decoders in flash analog-to-digital converters

Digital decoders in flash analog-to-digital converters are studied. An attractive approach for realizing the decoder is to count the ones in the thermometer coded comparator output with, e.g. a Wallace tree. Such an ones-counter can be fast and it incorporates global bubble error correction. We also suggest an improvement of the Wallace tree decoder, obtained by applying folding. This yields a decoder with less area and a circuit with shorter critical path, which should make it possible to design for lower power consumption than the Wallace tree decoder. The folded decoder also enables introduction of extra error correction circuitry for the same hardware cost, or less, as for the Wallace tree decoder, which does not have the extra bubble error correction. This makes the folded decoder not only attractive, but also to applications where low bit error rate is crucial.

Thermometer-to-binary decoders for flash analog-to-digital converters

Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder, corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.

Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters

The current-steering digital-to-analog converter (DAC) is the most common type of DAC for high-speed applications. Glitches present in the DAC output contribute to nonlinear distortion in the DAC transfer characteristics degrading the circuit performance. One source of glitches is asymmetry in the settling behavior when switching on and off a current source. A behavioral-level model of this nonideal behavior is derived in this work. Further, a method with low computational complexity for estimating the influence of the modeled errors in the frequency domain is developed. This method can be utilized by circuit designers to derive circuit requirements for fulfilling a given frequency-domain specification, potentially relaxing the requirements compared with a worst-case analysis. Examples of model utilization are given in terms of an analytical examination and MATLAB simulations. A good agreement between simulated and analytical results is obtained.

A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture

A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 μm × 120 μm. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.

Comparison of two thermometer-to-binary decoders for high-performance flash ADCs

The performance of flash analog-to-digital converters is affected significantly by the choice of thermometer-to-binary decoder topology. In this work two different promising decoder topologies, multiplexer-based and ones-counter, are evaluated. Two converters with different decoders, but otherwise similar, are therefore designed. Two test chips are also sent for manufacturing in a 130 nm silicon-on-insulator CMOS technology. The converter performance is evaluated by simulations using foundry provided models. The results show that both decoders can be used in high-speed converters, but the ones-counter decoder is more robust and yield a higher converter efficiency.

Dynamic element matching in D/A converters with restricted scrambling

Inaccurate matching of the analog sources in a D/A converter causes a signal-dependent error in the output. This distortion can be transformed into noise by assigning the digital control to the analog sources randomly, which is a technique referred to as dynamic element matching. In this paper, we present a dynamic element matching technique where the scrambling is restricted such that the glitches in the converter are minimized. By this, both the distortion due to glitches is reduced, and the signal-dependent error due to matching is suppressed. A hardware structure is proposed that implements the approach, and the operation of the hardware is described. Simulation results indicate that the method has a potential of yielding as good reduction of glitches as the optimal thermometer-coded converter and a signal-dependent error level that is almost as low as achieved with prior dynamic element matching techniques.

Time-Mode Analog-to-Digital Conversion Using Standard Cells

Synthesizable all-digital ADCs that can be designed, verified and taped out using a digital design flow are of interest due to a consequent reduction in design cost and an improved technology portability. As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. The proposed design is a time-mode circuit employing a VCO based multi-bit quantizer. The ADC has first order noise-shaping due to inherent error feedback of the oscillator and sinc anti-aliasing filtering due to continuous-time sampling. The proposed architecture employs a Gray-counter based quantizer design, which mitigates the problem of partial sampling of digital data in multi-bit VCO-based quantizers. Furthermore, digital correction employing polynomial-fit estimation is proposed to correct for VCO non-linearity. The design occupies 0.026 mm 2 when fabricated in a 65 nm CMOS process and delivers an ENOB of 8.1 bits over a signal bandwidth of 25.6 MHz, while sampling at 205 MHz. The performance is comparable to that of recently reported custom designed single-ended open-loop VCO-based ADCs, while being designed exclusively with standard cells, and consuming relatively low average power of 3.3 mW achieving an FoM of 235 fJ/step.

A strategy for reducing clock noise in mixed-signal circuits

Digital switching noise is of major concern in mixed-signal circuits due to the coupling of the noise via a shared substrate to the analog circuits. A significant noise source in this context is the digital clock network that generally has a high switching activity. There is a large capacitive coupling between the clock network and the substrate. Switching of the clock produces current peaks causing simultaneous switching noise (SSN). Sharp clock edges yields a high frequency content of the clock signal and a large SSN. High frequency noise is less attenuated through the substrate than low frequencies due to the parasitic inductance of the interconnect from on-chip to off-chip. In this work, we present a strategy that targets the problems with clock noise. The approach is to generate a clock with smooth edges, i.e. reducing both the high frequency components of the clock signal and the current peaks produced in the power supply. We use a special digital D flip-flop circuit that operates well with the clock. A test chip has been designed where we can control the rise and fall time of the clock edges in a digital FIR filter, and measure the performance of a fifth-order analog active-RC filter.