Jae Hoon Bong

Synthesis of ultrathin polymer insulating layers by initiated chemical vapour deposition for low-power soft electronics

Insulating layers based on oxides and nitrides provide high capacitance, low leakage, high breakdown field and resistance to electrical stresses when used in electronic devices based on rigid substrates. However, their typically high process temperatures and brittleness make it difficult to achieve similar performance in flexible or organic electronics. Here, we show that poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) prepared via a one-step, solvent-free technique called initiated chemical vapour deposition (iCVD) is a versatile polymeric insulating layer that meets a wide range of requirements for next-generation electronic devices. Highly uniform and pure ultrathin films of pV3D3 with excellent insulating properties, a large energy gap (>8 eV), tunnelling-limited leakage characteristics and resistance to a tensile strain of up to 4% are demonstrated. The low process temperature, surface-growth character, and solvent-free nature of the iCVD process enable pV3D3 to be grown conformally on plastic substrates to yield flexible field-effect transistors as well as on a variety of channel layers, including organics, oxides, and graphene.

Functionalized Graphene as an Ultrathin Seed Layer for the Atomic Layer Deposition of Conformal High-k Dielectrics on Graphene

Ultrathin functionalized graphene (FG) is demonstrated to work as an effective seed layer for the atomic layer deposition (ALD) of high-k dielectrics on graphene that is synthesized via chemical vapor deposition (CVD). The FG layer is prepared using a low-density oxygen plasma treatment on CVD graphene and is characterized using Raman spectroscopy and X-ray photoelectron spectroscopy (XPS). While the ALD deposition on graphene results in a patchy and rough dielectric deposition, the abundant oxygen species provided by the FG seed layer enable conformal and pinhole-free dielectric film deposition over the entire area of the graphene channel. The metal-insulator-graphene (MIG) capacitors fabricated with the FG-seeded Al2O3 exhibit superior scaling capabilities with low leakage currents when compared with the co-processed capacitors with Al seed layers.

Ultrathin graphene and graphene oxide layers as a diffusion barrier for advanced Cu metallization

We report on the diffusion barrier properties of chemical-vapor-deposition grown graphene, graphene oxide, and reduced graphene oxide (rGO) for copper metallization in integrated circuits. Single-layer graphene shows the best diffusion barrier performance among the three but it has poor integration compatibility, displaying weak adhesion and poor nucleation for Cu deposition on top of it. Within the allowable thermal budget in the back-end-of-line process, rGO in a range of 1 nm thickness shows excellent thermal stability with suitable integration compatibility at 400 °C for 30 min. The diffusion barrier property was verified through optical, physical, and chemical analyses. The use of an extremely thin rGO layer as a Cu barrier material is expected to provide an alternative route for further scaling of copper interconnect technology.

High performance graphene field effect transistors on an aluminum nitride substrate with high surface phonon energy

We demonstrate top-gate graphene field effect transistors (FETs) on an aluminum nitrite (AlN) substrate with high surface phonon energy. Electrical transport measurements reveal significant improvement of the carrier mobility of graphene FETs on AlN compared to those on SiO2. This is attributed to the suppression of surface phonon scattering due to the high surface phonon energy of the AlN substrate. The RF cut-off frequency of the graphene FET is also greatly increased when the AlN substrate is used. AlN can easily be formed on a Si or SiO2 substrate using a standard semiconductor process and thus provides a practical way to improve the performance of graphene FETs.

Work function tuning of metal/graphene stack electrode

Understanding of the contact between graphene and metal is a key issue to improve device performance. We extend the previous finding of work function pinning of monolayer graphene under various metals to multilayer graphene and discover that the work function of graphene under metal can be tuned from 4.3 eV to 5.1 eV by controlling the number of graphene layers. The work function of graphene is found to gradually shift with the number of graphene layers and four layers of graphene successfully screen this shift. These findings provide an alternative approach to control the work function of graphene electrodes.

Alleviation of fermi-level pinning effect at metal/germanium interface by the insertion of graphene layers

In this paper, we report the alleviation of the Fermi-level pinning on metal/n-germanium (Ge) contact by the insertion of multiple layers of single-layer graphene (SLG) at the metal/n-Ge interface. A decrease in the Schottky barrier height with an increase in the number of inserted SLG layers was observed, which supports the contention that Fermi-level pinning at metal/n-Ge contact originates from the metal-induced gap states at the metal/n-Ge interface. The modulation of Schottky barrier height by varying the number of inserted SLG layers (m) can bring about the use of Ge as the next-generation complementary metal-oxide-semiconductor material. Furthermore, the inserted SLG layers can be used as the tunnel barrier for spin injection into Ge substrate for spin-based transistors.

Improved Drain Current Saturation and Voltage Gain in Graphene-on-Silicon Field Effect Transistors.

Graphene devices for radio frequency (RF) applications are of great interest due to their excellent carrier mobility and saturation velocity. However, the insufficient current saturation in graphene field effect transistors (FETs) is a barrier preventing enhancements of the maximum oscillation frequency and voltage gain, both of which should be improved for RF transistors. Achieving a high output resistance is therefore a crucial step for graphene to be utilized in RF applications. In the present study, we report high output resistances and voltage gains in graphene-on-silicon (GoS) FETs. This is achieved by utilizing bare silicon as a supporting substrate without an insulating layer under the graphene. The GoSFETs exhibit a maximum output resistance of 2.5 MΩ∙μm, maximum intrinsic voltage gain of 28 dB, and maximum voltage gain of 9 dB. This method opens a new route to overcome the limitations of conventional graphene-on-insulator (GoI) FETs and subsequently brings graphene electronics closer to practical usage.

Wrinkle-free graphene with spatially uniform electrical properties grown on hot-pressed copper

The chemical vapor deposition (CVD) of graphene on Cu substrates enables the fabrication of large-area monolayer graphene on desired substrates. However, during the transfer of the synthesized graphene, topographic defects are unavoidably formed along the Cu grain boundaries, degrading the electrical properties of graphene and increasing the device-to-device variability. Here, we introduce a method of hot-pressing as a surface pre-treatment to improve the thermal stability of Cu thin film for the suppression of grain boundary grooving. The flattened Cu thin film maintains its smooth surface even after the subsequent high temperature CVD process necessary for graphene growth, and the formation of graphene without wrinkles is realized. Graphene field effect transistors (FETs) fabricated using the graphene synthesized on hot-pressed Cu thin film exhibit superior field effect mobility and significantly reduced device-to-device variation.

A quantitative strain analysis of a flexible single-crystalline silicon membrane

This study presents a quantitative strain analysis of a single-crystal Si membrane for high performance flexible devices. Advanced thinning and transfer methods were used to make flexible single-crystal Si devices. Two Si membrane strain gauges, each with a different stack, were fabricated on a polydimethylsiloxane/polyimide film using a silicon-on-insulator wafer. One gauge contains a 10-μm-thick handling Si layer, whereas the handling Si layer was completely removed for the other case. Although the Si membrane with the 10-μm-thick handling Si layer is flexible, the strain applied to the active Si layer (0.127%) is three times higher than the strain applied to the Si membrane without the handling Si layer (0.037%) at a bending radius of 5 mm. This leads to the more reliable electrical and mechanical performance of the device fabricated on the Si membrane without the handling Si layer. The experimental results were verified through a finite element method simulation and analytical modeling. The quantitati...

Vertically Formed Graphene Stripe for 3D Field-Effect Transistor Applications

A 100-nm wide, vertically formed graphene stripe (GS) is demonstrated for three-dimensional (3D) electronic applications. The GS forms along the sidewall of a thin nickel film. It is possible to further scale down the GS width by engineering the deposited thickness of the atomic layer deposition (ALD) Ni film. Unlike a conventional GS or graphene nanoribbon (GNR), the vertically formed GS is made without a graphene transfer and etching process. The process integration of the proposed GS FETs resembles that of currently commercialized vertical NAND flash memory with a design rule of less than 20 nm, implying practical usage of this formed GS for 3D advanced FET applications.